DECODING CONTROL WITH ADDRESS TRANSITION DETECTION IN PAGE ERASE FUNCTION

• US 20090185424A1
• Filed: 04/01/2009
• Published: 07/23/2009
• Est. Priority Date: 02/27/2007
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: PYEON, Hong Beom
• Granted Patent: US 7,778,107 B2
• Time in Patent Office: Days
• US Class Current: 365/185.120
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/20 Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access

Abstract

Circuits and methods are provided for controlling multi-page erase operations in flash memory. The page address of each address of a multi-page erase operation is latched in wordline decoders. A page select reset generator circuit processes the block addresses of each address of the multi-page erase operation. In the event the addresses relate to pages in different blocks, then previously latched page addresses are reset. This avoids the incorrect circuit operation that will result should a multi-page erase operation include multiple pages in different blocks.

Claims

1. An apparatus for limiting page erase operation in non-volatile memory, the apparatus comprising:

input circuitry for receiving block address portions of each address of a set of one or more addresses; and

a detector for detecting an address transition in response to the difference between the block address portions of two addresses of the set of page addresses, thereby producing a reset output for clearing latched pages.

2. A method for limiting page erase operation in non-volatile memory, the method comprising:

detecting the difference between the block address portions of a plurality of addresses;

resetting any previous selections of pages and blocks in response to the detected block address difference;

selecting a respective page in each of a plurality of blocks; and

selecting a respective one of the plurality of blocks.