High-Speed Receiver Architecture
First Claim
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1. A receiver comprising:
- an interleaved ADC having multiple ADC channels; and
a multi-channel equalizer coupled to the interleaved ADC, the multi-channel equalizer capable of applying different equalization to the different ADC channels, the multi-channel equalizer comprising;
a feedforward equalizer (FFE) coupled to a Viterbi decoder having a channel estimator, the channel estimator based on a Volterra series model of the channel.
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Abstract
A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.
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Citations
3 Claims
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1. A receiver comprising:
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an interleaved ADC having multiple ADC channels; and a multi-channel equalizer coupled to the interleaved ADC, the multi-channel equalizer capable of applying different equalization to the different ADC channels, the multi-channel equalizer comprising; a feedforward equalizer (FFE) coupled to a Viterbi decoder having a channel estimator, the channel estimator based on a Volterra series model of the channel. - View Dependent Claims (2, 3)
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Specification