Test Patterns for Detecting Misalignment of Through-Wafer Vias
First Claim
1. A method of determining a misalignment status of through-wafer vias, the method comprising:
- providing a semiconductor wafer;
forming a through-wafer via in the semiconductor wafer;
forming a plurality of conductive patterns adjacent to the through-wafer via, wherein a top surface of the through-wafer via and bottom surfaces of the plurality of conductive patterns are substantially coplanar; and
determining a connectivity between the through-wafer via and the plurality of conductive patterns.
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Abstract
A semiconductor chip including a test pattern is provided. The semiconductor chip includes a semiconductor substrate; a through-wafer via in the semiconductor substrate; and a plurality of conductive patterns over the semiconductor substrate and adjacent to each other. The bottom surfaces of the plurality of conductive patterns and a top surface of the through-wafer via are substantially coplanar. The through-wafer via is at least adjacent to the plurality of conductive patterns. The semiconductor chip further includes a plurality of bonding pads on a surface of the semiconductor chip, each being connected to one of the plurality of conductive patterns.
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Citations
20 Claims
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1. A method of determining a misalignment status of through-wafer vias, the method comprising:
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providing a semiconductor wafer; forming a through-wafer via in the semiconductor wafer; forming a plurality of conductive patterns adjacent to the through-wafer via, wherein a top surface of the through-wafer via and bottom surfaces of the plurality of conductive patterns are substantially coplanar; and determining a connectivity between the through-wafer via and the plurality of conductive patterns. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of forming a semiconductor wafer, the method comprising:
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providing the semiconductor wafer having a semiconductor substrate; forming a through-wafer via in the semiconductor substrate; forming a central conductive pattern substantially over the through-wafer via, wherein the through-wafer via has a top surface contacting a bottom surface of the central conductive pattern; forming a plurality of surrounding conductive patterns surrounding the central conductive pattern, wherein the central conductive pattern and the plurality of surrounding conductive patterns are coplanar; and forming a plurality of bonding pads on a surface of the semiconductor wafer, wherein each of the plurality of bonding pads is connected to one of the central conductive pattern and the plurality of surrounding conductive patterns. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A method of forming a semiconductor wafer, comprising:
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providing the semiconductor wafer having a semiconductor substrate; forming a through-wafer via in the semiconductor substrate, forming a plurality of surrounding conductive patterns substantially over a portion of the through-wafer via, at least one of the surrounding conductive patterns having a bottom surface contacting a top surface of the through-wafer via, wherein the plurality of surrounding conductive patterns are co-planar; and forming a plurality of bonding pads on the surface of the semiconductor wafer, at least one of the plurality of bonding pads being connected to one of the plurality of surrounding conductive patterns.
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Specification