METHOD FOR MANUFACTURING A CMOS DEVICE HAVING DUAL METAL GATE
First Claim
1. A method for manufacturing a CMOS device having dual metal gate comprising steps of:
- providing a substrate having a first conductive type transistor, a second conductive type transistor, and a dielectric layer covering the first conductive type transistor and the second conductive type transistor formed thereon;
planarizing the dielectric layer to expose gate conductive layers of a first gate of the first conductive type transistor and of a second gate of the second conductive type transistor;
forming a patterned blocking layer covering the second conductive type transistor and exposing the first conductive type transistor on the substrate;
performing a first etching process to remove the gate conductive layer of the first gate to form a first opening;
sequentially forming a first metal layer and a second metal layer in the first opening;
removing the patterned blocking layer covering the second conductive type transistor;
performing a second etching process to remove the gate conductive layer of the second gate to form a second opening; and
sequentially forming a third metal layer and a fourth metal layer in the second opening.
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Abstract
A method for manufacturing a CMOS device having dual metal gate includes providing a substrate having at least two transistors of different conductive types and a dielectric layer covering the two transistors, planarizing the dielectric layer to expose gate conductive layers of the two transistors, forming a patterned blocking layer exposing one of the conductive type transistor, performing a first etching process to remove a portion of a gate of the conductive type transistor, reforming a metal gate, removing the patterned blocking layer, performing a second etching process to remove a portion of a gate of the other conductive type transistor, and reforming a metal gate.
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Citations
20 Claims
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1. A method for manufacturing a CMOS device having dual metal gate comprising steps of:
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providing a substrate having a first conductive type transistor, a second conductive type transistor, and a dielectric layer covering the first conductive type transistor and the second conductive type transistor formed thereon; planarizing the dielectric layer to expose gate conductive layers of a first gate of the first conductive type transistor and of a second gate of the second conductive type transistor; forming a patterned blocking layer covering the second conductive type transistor and exposing the first conductive type transistor on the substrate; performing a first etching process to remove the gate conductive layer of the first gate to form a first opening; sequentially forming a first metal layer and a second metal layer in the first opening; removing the patterned blocking layer covering the second conductive type transistor; performing a second etching process to remove the gate conductive layer of the second gate to form a second opening; and sequentially forming a third metal layer and a fourth metal layer in the second opening. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification