Alternate Address Space to Permit Virtual Machine Monitor Access to Guest Virtual Address Space

• US 20090187726A1
• Filed: 11/18/2008
• Published: 07/23/2009
• Est. Priority Date: 01/22/2008
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Serebrin, Benjamin C., Haertel, Michael J.
• Application Number:
  US12/272,946
• Publication Number:
  US 20090187726A1
• Time in Patent Office: Days
• US Class Current: 711/202
• CPC Class Codes: G06F 9/455 Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
• CPC Class Codes: G06F 9/45537 Provision of facilities of other operating environments, e.g. WINE I/O emulation G06F13/105

Abstract

In one embodiment, a processor supports an alternate address space during execution of non-guest code (such as a minivisor or a virtual machine monitor (VMM)). The alternate address space may be the guest address space. An instruction in the minivisor/VMM may specify the alternate address space for a data access, permitting the minivisor/VMM to read guest memory state via the alternate address space. In another embodiment, a processor may implement a page table base address register dedicated for the minivisor'"'"'s use. In still another embodiment, the minivisor may be implemented as a specified entry point in the VMM address space.

Claims

1. A processor comprising:

one or more first registers configured to store first state defining a first address space mappable to a memory system to which the processor is coupled during use;

one or more second registers configured to store second state defining a second address space mappable to the memory system; and

an execution core coupled to the one or more first registers and the one or more second registers, and during execution of a guest under the control of a virtual machine monitor (VMM), the execution core is configured to use the first address space for data accesses generated by the guest, and during execution of non-guest code, the execution core is configured to select between the first address space and the second address space for a given data access generated by the non-guest code.

2. The processor as recited in claim 1 wherein the execution core is configured to use the first address space for a code fetch during execution of the guest.

3. The processor as recited in claim 2 wherein the execution core is configured to use the second address space for a code fetch during execution of the non-guest code.

4. The processor as recited in claim 1 wherein the execution core is configured to select between the first address space and the second address space responsive to an encoding of the instruction that generates the given data access.

5. The processor as recited in claim 4 wherein a presence of a segment override prefix byte in the instruction encoding causes the execution core to select the second address space.

6. The processor as recited in claim 5 wherein an absence of the segment override prefix byte in the instruction encoding causes the execution core to select the first address space.

7. The processor as recited in claim 6 wherein the segment override prefix byte is the code segment override prefix byte.

8. The processor as recited in claim 1 wherein the execution core is configured to select the first address space responsive to a specifically designated instruction, and wherein the execution core is configured to select the second address space responsive to other instructions.

9. The processor as recited in claim 1 wherein the execution core is configured to select between the first address space and the second address space responsive to a segment definition corresponding to a segment used by the instruction.

10. The processor as recited in claim 9 wherein the segment definition includes a segment type in a segment register that is used by the instruction.

11. The processor as recited in claim 1 wherein the one or more second registers store the first state during execution of the guest, and wherein the execution core is configured to move the state to the one or more first registers responsive to a guest exit from the guest.

12. The processor as recited in claim 1 wherein the execution core comprises translation circuitry configured to select the first address space as a current address space during execution of the guest.

13. The processor as recited in claim 12 wherein the translation circuitry is configured to select between the first address space as an alternate address space and the second address space as the current address space during execution of the non-guest code.

14. The processor as recited in claim 1 wherein the first state comprises at least one page table base address.

15. The processor as recited in claim 14 wherein the first state further comprises an address space identifier.

16. A method comprising:

during execution of a guest, using a first address space that is mappable to a system memory for data accesses generated by the guest;

detecting a guest exit to non-guest code;

responsive to the guest exit, establishing the first address space as an alternate address space useable by the non-guest code, the non-guest code also having a second address space mappable to the system memory as a current address space;

performing a first data access by the non-guest code, the performing including selecting the first address space for the first data access; and

performing a second data access by the non-guest code, the performing including selecting the second address space for the second data access.

17. The method as recited in claim 16 further comprising:

selecting the second address space for a code fetch during execution of the non-guest code; and

selecting the first address space for a code fetch during execution of the guest.

18. A computer accessible storage medium storing a plurality of instructions which, when executed:

generate a first data access using a first address space mappable to a system memory, the first address space also used by a guest that is controlled by the plurality of instructions; and

generate a second data access using a second address space mappable to the system memory, the second address space assigned to the plurality of instructions.

19. The computer accessible storage medium as recited in claim 18 wherein the first data access to accesses data that is used by the guest, and wherein the second data access accesses data that is not accessible to the guest.

20. A computer system comprising host hardware that includes at least one processor and a system memory, wherein the system memory stores at least one guest and a virtual machine monitor (VMM) during use, wherein the VMM controls execution of the guest, and wherein the processor supports a first address space during execution of the guest, and wherein the processor supports a second address space during execution of non-guest code, wherein the first address space and the second address space are mappable to the system memory, and wherein the processor further supports the first address space as an alternate address space during execution of the non-guest code, wherein the processor selects one of the first address space and the second address space for a data access generated during execution of the non-guest code.

21. The computer system as recited in claim 20 wherein the processor is configured to select between the first address space and the second address space responsive to an encoding of an instruction in the non-guest code that generates a given data access.

22. The computer system as recited in claim 20 wherein the processor is configured to select between the first address space and the second address space responsive to a segment type in a segment register associated with an instruction that generates a given data access.