Method and Apparatus for Improved Computer Load and Store Operations
First Claim
1. In computer operation, a method for selecting data entities from a memory and writing the data entities to a register file, comprising:
- consulting a first map of entities to copy relative to a first address;
selecting and reading those entities indicated by the map;
consulting a second map of positions to write the entities copied from the memory, relative to a first register; and
writing the entities to the register file according to the second map.
2 Assignments
0 Petitions
Accused Products
Abstract
Load and store operations in computer systems are extended to provide for Stream Load and Store and Masked Load and Store. In Stream operations, a CPU executes a Stream instruction that indicates, by appropriate arguments, a first address in memory or a first register in a register file from whence to begin reading data entities, and a first address or register from whence to begin storing the entities, and a number of entities to be read and written. In Masked Load and Masked Store operations stored masks are used to indicate patterns relative to first addresses and registers for loading and storing. Bit-string vector methods are taught for masks.
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Citations
45 Claims
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1. In computer operation, a method for selecting data entities from a memory and writing the data entities to a register file, comprising:
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consulting a first map of entities to copy relative to a first address; selecting and reading those entities indicated by the map; consulting a second map of positions to write the entities copied from the memory, relative to a first register; and writing the entities to the register file according to the second map. - View Dependent Claims (2, 3, 4, 5, 6)
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7. In computer operation, a method for selecting data entities from a register file and writing the data entities to a memory, comprising:
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consulting a first map of entities to read relative to a first register; selecting and reading those entities indicated by the map; consulting a second map of positions to write the entities read from the register file, relative to a first address; and writing the entities to the memory file according to the second map. - View Dependent Claims (8, 9, 10, 11)
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12. For use in computer operations, a Stream Load instruction comprising:
- an indication of the instruction;
a first argument indicating a first address in a memory from which to begin reading data entities; a second argument indicating a first register in a register file from which to write the data entities read from the memory; and a third argument indicating a number of data entities to be read and written.
- an indication of the instruction;
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13. For use in computer operations, a Masked Load instruction comprising:
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an indication of the instruction; a first argument indicating a first address in a memory at which to position a mask to indicate data entities to be read; a second argument indicating a first register in a register file beginning at which to write the data entities read from the memory; and a third argument indicating a mask number to be used to select the data entities to be read and written.
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14. For use in computer operations, a Masked Store instruction comprising:
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an indication of the instruction; a first argument indicating a first register in a register file at which to position a mask to indicate data entities to be read; a second argument indicating a first address in a memory beginning at which to write the data entities read from the register file; and a third argument indicating a mask number to be used to select the data entities to be copied and written.
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15. A computing system, comprising:
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a CPU; a memory; and a register file, characterized in that the CPU, in loading data entities from the memory into the register file, reads a predetermined number of data entities, and writes the data entities into registers of the register file in the same order as in the memory, beginning at a predetermined first register. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A computing system, comprising:
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a CPU; a memory; and a register file, characterized in that the CPU, in storing data entities into the memory from the register file, reads a predetermined number of data entities from the register file, and writes the data entities into addressed locations in memory in the same order as in the register file, beginning at a predetermined first address. - View Dependent Claims (22, 23, 24, 25, 26)
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27. A computing system, comprising:
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a CPU; a memory; and a register file; characterized in that the CPU, in loading data entities from the memory into the register file, enters the memory at a first address, reads data entities according to a pre-determined pattern relative to the first address, and writes the data entities into registers of the register file in a pre-determined pattern relative to a first register. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34)
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35. A computing system, comprising:
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a CPU; a memory; and a register file; characterized in that the CPU, in storing data entities into the memory from the register file, enters the register file at a first register, reads data entities from the register file according to a pre-determined pattern, and writes the data entities into addressed locations in memory also according to a pre-determined pattern, beginning at a first address. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42)
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43. A dynamic multistreaming processor, comprising:
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a first plurality k of individual streams; and a second plurality m of masks or mask sets, wherein individual masks or masks sets of the second plurality m are dedicated to exclusive use of individual ones of the first plurality of k streams for performing Masked Load and/or Masked Store operations. - View Dependent Claims (44)
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45. A dynamic multistreaming (DMS) processor system, comprising:
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a plurality k of individual streams; a set of masks or mask sets for use in performing Masked Load and Masked Store operations, wherein multiple data entities are loaded or stored as a result of executing a single instruction, and according to the masks; a cache memory; and a system memory, characterized in that the system, in performing a Masked Load or a Masked Store operation transfers data entities directly between the system memory and one or more register files.
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Specification