Method and Apparatus for Improved Computer Load and Store Operations

• US 20090187739A1
• Filed: 03/26/2009
• Published: 07/23/2009
• Est. Priority Date: 12/16/1998
• Status: Abandoned Application

• Current Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Original Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Inventors: Melvin, Stephen, NEMIROVSKY, Mario, Sankar, Narendra, Musoll, Enrique
• Application Number:
  US12/411,913
• Publication Number:
  US 20090187739A1
• Time in Patent Office: Days
• US Class Current: 712/204
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction

Abstract

Load and store operations in computer systems are extended to provide for Stream Load and Store and Masked Load and Store. In Stream operations, a CPU executes a Stream instruction that indicates, by appropriate arguments, a first address in memory or a first register in a register file from whence to begin reading data entities, and a first address or register from whence to begin storing the entities, and a number of entities to be read and written. In Masked Load and Masked Store operations stored masks are used to indicate patterns relative to first addresses and registers for loading and storing. Bit-string vector methods are taught for masks.

Claims

1. In computer operation, a method for selecting data entities from a memory and writing the data entities to a register file, comprising:

consulting a first map of entities to copy relative to a first address;

selecting and reading those entities indicated by the map;

consulting a second map of positions to write the entities copied from the memory, relative to a first register; and

writing the entities to the register file according to the second map.

2. The method of claim 1, wherein the steps follow from a Masked Load instruction implemented according to an instruction set architecture (ISA).

3. The method of claim 2, wherein the ISA is MIPS.

4. The method of claim 3, wherein arguments of the Masked Load instruction indicate a beginning memory address for positioning a mask, a mask number to be used, and a first register where to begin writing data entities in the register file.

5. The method of claim 1, wherein the first and second maps are implemented as bit strings, wherein the position of bits in the string indicate the positions for data entities to be selected from memory, and the registers to which data entities are to be written.

6. The method of claim 2, wherein the execution of the Masked Load is performed in a Dynamic Multi-streaming (DMS) processor by a first stream running a first thread, and the first stream remains inactive while the Masked Load instruction is executed.

7. In computer operation, a method for selecting data entities from a register file and writing the data entities to a memory, comprising:

consulting a first map of entities to read relative to a first register;

selecting and reading those entities indicated by the map;

consulting a second map of positions to write the entities read from the register file, relative to a first address; and

writing the entities to the memory file according to the second map.

8. The method of claim 7, wherein the steps follow from a Masked Store instruction implemented according to an instruction set architecture (ISA).

9. The method of claim 8, wherein the ISA is MIPS.

10. The method of claim 9, wherein arguments of the Masked Store instruction indicate a beginning register for positioning a mask, a mask a number to be used, and a first register where to begin writing data entities in the memory.

11. The method of claim 7, wherein the first and second maps are implemented as bit strings, wherein the position of bits in the string indicate the positions for data entities to be read, and the registers to which data entities are to be written.

12. For use in computer operations, a Stream Load instruction comprising:

an indication of the instruction;

a first argument indicating a first address in a memory from which to begin reading data entities;

a second argument indicating a first register in a register file from which to write the data entities read from the memory; and

a third argument indicating a number of data entities to be read and written.

13. For use in computer operations, a Masked Load instruction comprising:

an indication of the instruction;

a first argument indicating a first address in a memory at which to position a mask to indicate data entities to be read;

a second argument indicating a first register in a register file beginning at which to write the data entities read from the memory; and

a third argument indicating a mask number to be used to select the data entities to be read and written.

14. For use in computer operations, a Masked Store instruction comprising:

an indication of the instruction;

a first argument indicating a first register in a register file at which to position a mask to indicate data entities to be read;

a second argument indicating a first address in a memory beginning at which to write the data entities read from the register file; and

a third argument indicating a mask number to be used to select the data entities to be copied and written.

15. A computing system, comprising:

a CPU;

a memory; and

a register file,

characterized in that the CPU, in loading data entities from the memory into the register file, reads a predetermined number of data entities, and writes the data entities into registers of the register file in the same order as in the memory, beginning at a predetermined first register.

16. The system of claim 15, wherein the transferring of data entities from memory into the register file follow from a Stream Load instruction implemented according to an instruction set architecture (ISA) and executed by the CPU.

17. The system of claim 16, wherein the ISA is MIPS.

18. The system of claim 17, wherein arguments of the Stream Load instruction indicate a beginning memory address from which to read data entities, a first register in the register file from which to write the data entities, and a number indicating the number of data entities to read and write.

19. The system of claim 16, wherein the execution of the Stream Load is performed in a Dynamic Multi-streaming (DMS) processor by a first stream running a first thread, and the first stream remains inactive while the Stream Load instruction is executed.

20. The system of claim 16, wherein the execution of the Stream Load is performed in a Dynamic Multi-streaming (DMS) processor by a first stream running a first thread, and the first stream executes instructions that do not depend on values in memory affected by the Stream Load instruction while the Stream Load instruction is executed.

21. A computing system, comprising:

a CPU;

a memory; and

a register file,

characterized in that the CPU, in storing data entities into the memory from the register file, reads a predetermined number of data entities from the register file, and writes the data entities into addressed locations in memory in the same order as in the register file, beginning at a predetermined first address.

22. The system of claim 21, wherein the storing of data entities from the register file into memory follows from a Stream Store instruction implemented according to an instruction set architecture (ISA) and executed by the CPU.

23. The system of claim 22, wherein the ISA is MIPS.

24. The system of claim 23, wherein arguments of the Stream Store instruction indicate a first register file from which to read data entities, a first address in memory to which to write the data entities, and a number indicating the number of data entities to read and write.

25. The system of claim 22, wherein the execution of the Stream Store is performed in a Dynamic Multi-streaming (DMS) processor by a first stream running a first thread, and the first stream remains inactive while the Stream Store instruction is executed.

26. The system of claim 22, wherein the execution of the Stream Store is performed in a Dynamic Multi-streaming (DMS) processor by a first stream running a first thread, and the first stream executes instructions that do not depend on values in memory affected by the Stream Store instruction while the Stream Store instruction is executed.

27. A computing system, comprising:

a CPU;

a memory; and

a register file;

characterized in that the CPU, in loading data entities from the memory into the register file, enters the memory at a first address, reads data entities according to a pre-determined pattern relative to the first address, and writes the data entities into registers of the register file in a pre-determined pattern relative to a first register.

28. The system of claim 27, wherein the loading of data entities from memory into the register file follows from a Masked Load instruction implemented according to an instruction set architecture (ISA) and executed by the CPU.

29. The system of claim 28, wherein the ISA is MIPS.

30. The system of claim 29, wherein arguments of the Masked Load instruction indicate a beginning memory address from which to read data entities, a first register in the register file beginning at which to write the data entities, and a Mask Number indicating a stored mask to be employed to indicate the relative positions in the memory and register file for reading a writing data entities.

31. The system of claim 30, wherein the stored masks are implemented as two bit-string vectors, a first vector indicating which data entities relative to the first address to read, and the second indicating into which registers relative to the first register to write the data entities.

32. The method of claim 31, wherein bit string maps are expressed as sub-masks, and sub masks are linkable in different combinations to provide combined masks.

33. The system of claim 29, wherein the execution of the Masked Load is performed in a Dynamic Multi-streaming (DMS) processor by a first stream running a first thread, and the first stream remains inactive while the Stream Load instruction is executed.

34. The system of claim 29, wherein the execution of the Masked Load is performed in a Dynamic Multi-streaming (DMS) processor by a first stream running a first thread, and the first stream executes instructions that do not depend on values in memory affected by the Masked Load instruction while the Masked Load instruction is executed.

35. A computing system, comprising:

a CPU;

a memory; and

a register file;

characterized in that the CPU, in storing data entities into the memory from the register file, enters the register file at a first register, reads data entities from the register file according to a pre-determined pattern, and writes the data entities into addressed locations in memory also according to a pre-determined pattern, beginning at a first address.

36. The system of claim 35, wherein the storing of data entities from the register file into memory follows from a Masked Store instruction implemented according to an instruction set architecture (ISA) and executed by the CPU.

37. The system of claim 36, wherein the ISA is MIPS.

38. The system of claim 37, wherein arguments of the Masked Store instruction indicate a beginning memory address from which to read data entities, a first register in the register file beginning at which to write the data entities, and a Mask Number indicating a stored mask to be employed to indicate the relative positions in the memory and register file for reading and writing the data entities.

39. The system of claim 38, wherein the stored masks are implemented as two bit-string vectors, a first vector indicating which data entities relative to the first register to read, and the second indicating into which registers relative to the first address to write the data entities.

40. The method of claim 39, wherein bit string maps are expressed as sub-masks, and sub masks are linkable in different combinations to provide combined masks.

41. The system of claim 36, wherein the execution of the Masked Store Load is performed in a Dynamic Multi-streaming (DMS) processor by a first stream running a first thread, and the first stream remains inactive while the Stream Load instruction is executed.

42. The system of claim 36, wherein the execution of the Masked Store is performed in a Dynamic Multi-streaming (DMS) processor by a first stream running a first thread, and the first stream executes instructions that do not depend on values in memory affected by the Masked Store instruction while the Masked Store instruction is executed.

43. A dynamic multistreaming processor, comprising:

a first plurality k of individual streams; and

a second plurality m of masks or mask sets,

wherein individual masks or masks sets of the second plurality m are dedicated to exclusive use of individual ones of the first plurality of k streams for performing Masked Load and/or Masked Store operations.

44. The DMS processor of claim 43, wherein individual masks or mask sets are amendable only by the stream to which the individual mask or mask sets are dedicated.

45. A dynamic multistreaming (DMS) processor system, comprising:

a plurality k of individual streams;

a set of masks or mask sets for use in performing Masked Load and Masked Store operations, wherein multiple data entities are loaded or stored as a result of executing a single instruction, and according to the masks;

a cache memory; and

a system memory,

characterized in that the system, in performing a Masked Load or a Masked Store operation transfers data entities directly between the system memory and one or more register files.