Data processing apparatus and method for instruction pre-decoding

• US 20090187743A1
• Filed: 01/23/2008
• Published: 07/23/2009
• Est. Priority Date: 01/23/2008
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Greenhalgh, Peter Richard
• Granted Patent: US 8,037,286 B2
• Time in Patent Office: Days
• US Class Current: 712/213
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/30196 using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/3865 using deferred exception handling, e.g. exception flags

Abstract

The present invention provides a data processing apparatus comprising processing circuitry for executing a sequence of instructions and pre-decoding circuitry for receiving the instructions fetched from memory. The pre-decoding circuitry performs a pre-decoding operation to generate corresponding pre-decoded instructions and stores them in a cache for access by the processing circuitry. For each instruction fetched from the memory, the pre-decoding circuitry detects whether the instruction is an abnormal instruction and upon such detection provides in association with a corresponding pre-decoded instruction an identifier identifying that instruction as abnormal.

Claims

1. A data processing apparatus comprising:

processing circuitry for executing a sequence of instructions;

pre-decoding circuitry for receiving the instructions fetched from memory and performing a pre-decoding operation to generate corresponding pre-decoded instructions;

a cache for storing the pre-decoded instructions for access by said processing circuitry;

wherein the pre-decode operation, for each instruction fetched from the memory, detects whether the instruction is an abnormal instruction and upon such detection provides in association with a corresponding pre-decoded instruction an identifier identifying that instruction as abnormal.

2. A data processing apparatus as claimed in claim 1, wherein said abnormal instruction is an undefined instruction.

3. A data processing apparatus as claimed in claim 1, wherein said abnormal instruction is an unpredictable instruction.

4. A data processing apparatus as claimed in claim 1, wherein said identifier comprises side band bits in said corresponding pre-decoded instruction.

5. A data processing apparatus as claimed in claim 4, wherein said side band bits are appended to said corresponding pre-decoded instruction.

6. A data processing apparatus as claimed in claim 4, wherein said side band bits are inserted into said corresponding pre-decoded instruction.

7. A data processing apparatus as claimed in claim 4, wherein said side band bits replace redundant bits in said corresponding pre-decoded instruction.

8. A data processing apparatus as claimed in claim 2, wherein said identifier identifies said abnormal instruction as undefined.

9. A data processing apparatus as claimed in claim 3, wherein said identifier identifies said abnormal instruction as unpredictable.

10. A data processing apparatus as claimed in claim 1, wherein said identifier identifies said abnormal instruction as undefined irrespective of a type of the abnormal instruction.

11. A data processing apparatus as claimed in claim 1, wherein the pre-decode operation converts said abnormal instruction into a predetermined undefined instruction.

12. A data processing apparatus as claimed in claim 1, wherein upon encountering said corresponding pre-decoded instruction said processing circuitry is configured to execute said abnormal instruction in a predetermined manner.

13. A data processing apparatus as claimed in claim 12, wherein said predetermined manner comprises executing said corresponding pre-decoded instruction such that a state of the data processing apparatus is not altered.

14. A data processing apparatus as claimed in claim 12, wherein said predetermined manner comprises triggering an exception.

15. A method of processing data comprising the steps of:

fetching instructions from memory;

performing a pre-decoding operation on said fetched instructions to generate corresponding pre-decoded instructions, wherein said pre-decoding operation comprises, for each instruction fetched from the memory, detecting whether the instruction is an abnormal instruction and upon such detection providing in association with a corresponding pre-decoded instruction an identifier identifying that instruction as abnormal; and

storing the pre-decoded instructions in a cache for access by said processing circuitry.

16. A data processing apparatus comprising:

processing means for executing a sequence of instructions;

pre-decoding means for receiving the instructions fetched from memory means and performing a pre-decoding operation to generate corresponding pre-decoded instructions;

cache means for storing the pre-decoded instructions for access by said processing means;

wherein the pre-decode operation, for each instruction fetched from the memory means, detects whether the instruction is an abnormal instruction and upon such detection provides in association with a corresponding pre-decoded instruction an identifier identifying that instruction as abnormal.