Common test logic for multiple operation modes

• US 20090187799A1
• Filed: 01/23/2008
• Published: 07/23/2009
• Est. Priority Date: 01/23/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Zhang, Ming, Wu, David M., Jaber, Talal
• Granted Patent: US 7,734,972 B2
• Time in Patent Office: Days
• US Class Current: 714/727
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/31858 Delay testing
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

In one embodiment, the present invention includes a processor having a plurality of logical units to perform operations on data. Each unit may include a multiple input shift register (MISR) at an input of the logical unit to collect and compress data from input signals to the unit. In turn, each MISR may includes bit cells, each having a first cell to receive incoming data and controlled by a first clock signal, a second cell to receive an output of the first cell and controlled by a second clock signal, a mask cell to receive an output of the second cell and to generate a mask signal responsive to a mask clock signal, and a multiplexer coupled between the first and second cells. Other embodiments are described and claimed.

Claims

1. An apparatus comprising:

a processor having a plurality of logical units to perform operations on data, wherein each of the logical units includes a multiple input shift register (MISR) at an input of the logical unit to collect and compress data from a plurality of input signals to the logical unit, wherein the MISR is a common test structure to perform design for test (DFT) operations, reliability-availability-serviceability (RAS) operations, structured based functional test (SBFT) operations and debug operations, wherein the plurality of MISRs are configured as a scan chain having a first MISR coupled to an output of a test access port (TAP) controller and a last MISR coupled to an input of the TAP controller.

2. The apparatus of claim 1, wherein the MISR is to receive a corresponding one of the plurality of input signals from each of a plurality of flops coupled at an input of the logical unit, the plurality of flops to further provide the plurality of input signals to functional units of the logical unit.

3. The apparatus of claim 1, wherein the MISR is to receive an enable signal and a load signal from the TAP controller.

4. The apparatus of claim 3, wherein the MISR includes a plurality of bit cells, each bit cell having a first cell to receive incoming data and controlled by a first clock signal, a second cell to receive an output of the first cell and controlled by a second clock signal, and a mask cell to receive an output of the second cell and to generate a mask signal responsive to a mask clock signal.

5. The apparatus of claim 4, wherein the first cell, the second cell, and the mask cell each comprise a flop.

6. The apparatus of claim 4, further comprising a first logic gate to receive the output of the second cell and an output of a second logic gate, the second logic gate to receive the output of the mask cell and an incoming data bit of one of the plurality of input signals, the first logic gate to compress the incoming data bit.

7. The apparatus of claim 6, further comprising a multiplexer coupled between the first cell and the second cell, the multiplexer to provide the output of the first cell in a DFT mode and to provide the incoming data bit in a RAS mode, wherein the incoming data bit provided to the second logic gate is delayed from the incoming data bit provided to the second cell.

8. The apparatus of claim 6, wherein an output of the first logic gate is to be provided to an error recovery mechanism in the RAS mode, the output of the first logic gate indicative of an error in a flop that provides the incoming data bit to the second logic gate.

9. The apparatus of claim 4, further comprising a first clock generator to generate the first clock signal, the first clock generator including a first finite state machine (FSM) to detect a falling edge of a test clock, and first logic to receive a control signal from the first FSM and the load signal and the enable signal from the TAP controller and to generate the first clock signal therefrom.

10. The apparatus of claim 9, further comprising a second clock generator to generate the second clock signal, the second clock generator including a second finite state machine (FSM) to detect a rising edge of the test clock, wherein the first clock signal and the second clock signal are non-overlapping.

11. A system comprising:

a processor having a plurality of logical units to perform operations on data, where each of the logical units includes a multiple input shift register (MISR) at an input of the logical unit to collect and compress data from a plurality of input signals to the logical unit, each MISR including a plurality of bit cells, each bit cell having a first cell to receive incoming data and controlled by a first clock signal, a second cell to receive an output of the first cell and controlled by a second clock signal, a mask cell to receive an output of the second cell and to generate a mask signal responsive to a mask clock signal, and a multiplexer coupled between the first cell and the second cell to provide the output of the first cell in a first mode and to provide a data bit from a different logical unit in a second mode; and

a dynamic random access memory (DRAM) coupled to the processor.

12. The system of claim 11, wherein the MISR is a common test structure to perform design for test (DFT) operations in the first mode, reliability-availability-serviceability (RAS) operations in the second mode, structured based functional test (SBFT) operations and debug operations.

13. The system of claim 11, further comprising a first logic gate to receive the output of the second cell and an output of a second logic gate, the second logic gate to receive the output of the mask cell and the data bit, the first logic gate to compress the data bit, wherein the data bit provided to the second logic gate is delayed from the data bit provided to the second cell.

14. The system of claim 11, further comprising a first clock generator to generate the first clock signal, the first clock generator including a first finite state machine (FSM) to detect a falling edge of a test clock, and first logic to receive a control signal from the first FSM and control signals from a test access port (TAP) controller, and a second clock generator to generate the second clock signal, the second clock generator including a second FSM to detect a rising edge of the test clock, wherein the first clock signal and the second clock signal are non-overlapping.

15. The system of claim 11, wherein a snapshot of a state of an internal node of the processor may be taken over a first clock cycle and a second clock cycle via the first cell and the second cell.