Interconnection element for electric circuits

• US 20090188706A1
• Filed: 12/23/2008
• Published: 07/30/2009
• Est. Priority Date: 12/25/2007
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Tessera Interconnect Materials Incorporated (Adeia Inc.)
• Inventors: Endo, Kimitaka
• Granted Patent: US 8,299,368 B2
• Time in Patent Office: Days
• US Class Current: 174/257
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/13609 Indium [In] as principal constituent
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01R 43/0256 for soldering or welding connectors to a printed circuit board
• CPC Class Codes: H05K 1/185 Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/0355 Metal foils
• CPC Class Codes: H05K 2201/0361 Etched tri-metal structure, i.e. metal layers or metal patterns on both sides of a different central metal layer which is later at least partly etched
• CPC Class Codes: H05K 2201/10674 Flip chip
• CPC Class Codes: H05K 2203/0384 Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
• CPC Class Codes: H05K 2203/0542 Continuous temporary metal layer over metal pattern
• CPC Class Codes: H05K 3/06 the conductive material being removed chemically or electrolytically, e.g. by photo-etch process semi-additive methods H05K3/108
• CPC Class Codes: H05K 3/4007 Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457
• CPC Class Codes: H05K 3/4015 using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
• CPC Class Codes: H05K 3/4614 the electrical connections between the circuit boards being made during lamination

Abstract

An interconnection element and method for making same is disclosed. The interconnection element may include a plurality of metal conductors, a plurality of solid metal bumps and a low melting point (LMP) metal layer. The solid metal bumps overly and project in a first direction away from respective ones of the conductors. Each bump has at least one edge bounding the bump in at least a second direction transverse to the first direction. The low melting point (LMP) metal layer has a first face joined to the respective ones of the conductors and bounded in the second direction by at least one edge and a second face joined to the bumps. The edges of the bumps and the LMP layer are aligned in the first direction, and the LMP metal layer has a melting temperature substantially lower than the conductors.

Claims

1. An interconnection element comprising:

a plurality of metal conductors;

a plurality of solid metal bumps overlying and projecting in a first direction away from respective ones of the conductors, each bump having at least one edge bounding the bump in at least a second direction transverse to the first direction; and

a low melting point (LMP) metal layer having a first face joined to the respective ones of the conductors and bounded in the second direction by at least one edge and a second face joined to the bumps,

wherein the edges of the bumps and the LMP layer are aligned in the first direction, and

wherein the LMP metal layer has a melting temperature substantially lower than the conductors.

2. The interconnection element of claim 1, further comprising a dielectric element extending in the second direction and in a third direction transverse to the first direction, wherein the plurality of metal conductors extend in the second and third directions.

3. The interconnection element of claim 1, wherein the LMP metal layer is selected from the tin metal group consisting of tin, tin-copper, tin-lead, tin-zinc, tin-bismuth, tin-indium, tin-silver-copper, tin-zinc-bismuth, and tin-silver-indium-bismuth.

4. The interconnection element of claim 1, wherein the LMP metal layer is comprised of a gallium series metal including gallium and a metal selected from the group consisting of zinc, tin, indium, bismuth, copper, nickel, cobalt, and gold.

5. The interconnection element of claim 1, wherein the bumps are capable of being electrically connected to a separate printed circuit board or an electronic circuit component, and wherein the melting temperature of the LMP metal layer is not reached during connection of the bumps to the separate printed circuit board or electronic circuit component.

6. The interconnection element of claim 1, further comprising a protection layer overlying the metal bumps and a metal connection contacting the bump so as to provide for electrical connection to a circuit panel or an electronic circuit component,

wherein the metal connection is capable of being reflowed, and wherein the LMP metal layer has a first melting point capable of melting during the reflow process, and

wherein the protection layer has a second melting point greater than the melting point of the LMP metal layer.

7. The interconnection element according to claim 6, wherein the metal connection is a solder connection including a solder ball disposed to cover at least a part of the bumps.

8. The interconnection element of claim 1, further comprising a dielectric element underlying the metal conductors and at least a portion of the LMP metal layer.

9. The interconnection element of claim 2, further comprising a circuit panel having conductive pads, the metal bumps being joined to the conductive pads of the circuit panel.

10. The interconnection element of claim 9, wherein the circuit panel is a printed circuit board.

11. The interconnection element of claim 1, wherein the LMP metal layer is comprised of copper and includes first and second faces and a plurality of layers or portions of variable compositions extending between the first and second faces, and wherein at least one of the plurality of layers or portions has a higher copper concentration than a layer positioned adjacent thereto.

12. The interconnection element of claim 1, further comprising a microelectronic element connected to the interconnection element, the microelectronic element having first and second outer edges, an encapsulant joined to the microelectronic element extending beyond the first and second outer edges, and a via extending through a portion of the encapsulant adjacent the first or the second edge of the chip.

13. The interconnection element of claim 12, wherein the via further includes a plated through hole.

14. A method of fabricating an interconnection element comprising:

joining a metal foil extending in first and second directions with a plurality of metal conductors and a low melting point (LMP) metal layer separating the sheet from the conductors; and

patterning the metal foil to form a plurality of solid metal bumps extending away from the LMP metal layer in a third direction transverse to the first and second directions,

wherein edges of the metal bumps in the first and second directions are aligned with corresponding edges of the LMP metal layer, and

wherein the LMP metal layer has a melting temperature substantially lower than the conductors.

15. The method of fabricating the interconnection element of claim 14, further comprising removing portions of the LMP metal layer exposed between the metal bumps.

16. The method of fabricating the interconnection element of claim 14, further comprising joining the LMP metal layer to a dielectric element, wherein the conductors separate at least a portion of the LMP metal layer from the dielectric element.

17. The method of fabricating the interconnection element of claim 16, wherein the LMP metal foil is comprised of copper or copper alloy.

18. The method of fabricating the interconnection element of claim 14, wherein the step of joining the metal foil to the LMP metal layer includes pressing the metal foil onto the LMP metal layer.

19. The method of fabricating the interconnection element of claim 16, wherein the LMP metal layer is joined to the dielectric layer and conductors by a technique selected from the group consisting of electroless plating, electroplating, displacement plating, hot air solder leveling, and cladding.

20. The method of fabricating the interconnection element of claim 14, further including removing portions of the LMP metal layer,

wherein the step of forming the plurality of bumps includes etching the metal foil using a first etchant having a first etching rate with respect to the metal foil and a second etching rate with respect to the LMP metal layer, the second etching rate being less than the first etching rate or zero, and

wherein the step of removing the LMP metal layer includes etching the LMP metal layer using a second etchant having a third etching rate with respect to the metal of the LMP metal layer and a fourth etching rate with respect to the metal, the fourth etching rate being less than the third etching rate or zero.

21. The method of fabricating the interconnection element of claim 20, wherein the first etchant is an alkaline etching solution, and the second etchant is an acid etching solution.

22. The method of fabricating the interconnection element of claim 14, wherein the LMP metal layer includes tin.

23. The method of fabricating the interconnection element of claim 14, further comprising joining conductive pads of a microelectronic element to the metal bumps, forming an encapsulant contacting edges and at least one face of the microelectronic element and a conductive via extending through the encapsulant.

24. The method of fabricating the interconnection element of claim 23, wherein the via is formed by a process including plating an inner wall of a hole extending through the encapsulant.