Organic transistor comprising a self-aligning gate electrode, and method for the production thereof

• US 20090189147A1
• Filed: 01/13/2005
• Published: 07/30/2009
• Est. Priority Date: 01/14/2004
• Status: Abandoned Application

• Current Assignee: PolyIC GmbH & Co. KG (Leonhard KURZ Stiftung & Company KG)
• Original Assignee: PolyIC GmbH & Co. KG (Leonhard KURZ Stiftung & Company KG)
• Inventors: Fix, Walter, Ficker, Jürgen
• Application Number:
  US10/585,775
• Publication Number:
  US 20090189147A1
• Time in Patent Office: Days
• US Class Current: 257/40
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H10K 10/464 Lateral top-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 71/30 Doping active layers, e.g. electron transporting layers
• CPC Class Codes: H10K 71/60 Forming conductive regions or layers, e.g. electrodes

Abstract

An unpatterned semiconductor layer is applied to a substrate for the production of an organic transistor. An insulator is arranged on the semiconductor layer wherein at least the insulator layer is patterned, so that at least source and drain electrode layers can be formed subsequently. The source and drain electrode layers are formed after the patterning of at least the insulator layer to ensures that an overlap of both a gate electrode layer and the source and drain electrode layers is essentially avoided.

Claims

1. A method for the production of an organic transistor including a substrate with at least one unpatterned semiconductor layer on the substrate and an unpatterned insulator layer on the semiconductor layer;

the method comprising;

patterning of at least the insulator layer; and

forming at least source and drain electrode layers coupled to the semiconductor layer after the patterning of the insulator layer.

2. The method as claimed in claim 1 wherein an unpatterned gate electrode layer is on the insulator layer;

the method comprising;

jointly patterning the insulator layer and the gate electrode layer to uncover regions of the semiconductor layer; and

the forming the source and drain electrode layers is by doping the uncovered regions of the semiconductor layer.

3. The method as claimed in claim 2 wherein the doping of the uncovered regions of the semiconductor layer is performed with a doping chemical.

4. The method as claimed in claim 1 wherein an unpatterned gate electrode layer is on the insulator layer,

the method comprising:

jointly patterning the semiconductor layer, the insulator layer and the gate electrode layer to uncover regions of the substrate,

the forming of the source and drain electrode layers is by application of a conductive substance to the uncovered regions of the substrate.

5. The method as claimed in claim 1

including jointly patterning the semiconductor layer and the insulator layer so that regions of the substrate are uncovered;

and

the forming of the source and drain electrodes is by joint formation of the source and drain electrode layers and of a gate electrode layer by application of a conductive substance to the uncovered regions of the substrate and to the insulator layer.

6. The method as claimed in claim 1 wherein the source and drain electrode layers are formed such that they do not overlap the gate electrode layer.

7. The method as claimed in claim 1 wherein the patterning is carried out by a laser, a lithographic process or a printing lithographic process.

9. The method as claimed in claim 1 wherein the semiconductor layer is formed from an organic semiconducting substance.

10. The method as claimed in claim 1 wherein the insulator layer is formed from an organic electrically insulating substance.

11. An organic transistor made with the method of any one of claims 1 to 10.

8. The method as claimed in 1 wherein the substrate is a plastic film.