SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

• US 20090189219A1
• Filed: 11/25/2008
• Published: 07/30/2009
• Est. Priority Date: 01/30/2008
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: SHINBORI, Atsushi, Nakazawa, Yoshito
• Granted Patent: US 8,129,780 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 : with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

The present invention provides a technique capable of attaining an improvement in current detection accuracy in a trench gate type power MISFET equipped with a current detection circuit. Inactive cells are disposed so as to surround the periphery of a sense cell. That is, the inactive cell is provided between the sense cell and an active cell. All of the sense cell, active cell and inactive cells are respectively formed of a trench gate type power MISFET equipped with a dummy gate electrode. At this time, the depth of each trench extends through a channel forming region and is formed up to the deep inside (the neighborhood of a boundary with a semiconductor substrate) of an n-type epitaxial layer. Further, a p-type semiconductor region is provided at a lower portion of each trench. The p-type semiconductor region is formed so as to contact the semiconductor substrate.

Claims

1. A semiconductor device comprising:

(a) an active cell which causes a load current to flow therethrough;

(b) a sense cell which detects a magnitude of the load current flowing through the active cell; and

(c) an inactive cell which separates the active cell and the sense cell from each other,

wherein each of the active cell, the sense cell and the inactive cell includes;

(d1) a first semiconductor region of a first conduction type formed over a first surface of a semiconductor substrate corresponding to the first conduction type;

(d2) a second semiconductor region of a second conduction type corresponding to a conduction type opposite to the first conduction type, said second semiconductor region being formed over the first semiconductor region;

(d3) a trench which penetrates the second semiconductor region to reach the first semiconductor region and is formed so as not to reach the semiconductor substrate;

(d4) a first insulating film formed in parts of a bottom face of the trench and a side surface thereof;

(d5) a dummy gate electrode formed inside the trench via the first insulating film;

(d6) a second insulating film formed so as to cover an upper portion of the dummy gate electrode;

(d7) a gate electrode provided over the second insulating film and formed inside the trench;

(d8) a gate insulating film formed between the side surface of the trench and the gate electrode; and

(d9) a drain region comprising the semiconductor substrate corresponding to the first conduction type, and

wherein (d10) each of the active cell and the sense cell further has a source region formed in alignment with the trench and comprising a semiconductor region of the first conduction type formed over the second semiconductor region, whereas the inactive cell does not include the source region.

2. The semiconductor device according to claim 1, wherein the dummy gate electrode and the gate electrode are electrically coupled to each other.

3. The semiconductor device according to claim 1,

wherein the trench with the dummy gate electrode and the gate electrode embedded therein is formed in plural form so as to be arranged in a first direction of the semiconductor substrate, and

wherein the respective trenches are formed so as to extend in a second direction orthogonal to the first direction.

4. The semiconductor device according to claim 3, wherein first trenches of the respective trenches which extend in the second direction through an active cell forming area formed with the active cell, a sense cell forming area formed with the sense cell and an inactive cell forming area formed with the inactive cell, exist.

5. The semiconductor device according to claim 4, wherein gate electrodes embedded in the first trenches extending in the second direction through the active cell forming area, the sense cell forming area and the inactive cell forming area function as a gate electrode of the active cell in the active cell forming area, function as a gate electrode of the sense cell in the sense cell forming area, and function as a gate electrode of the inactive cell in the inactive cell forming area, respectively.

6. The semiconductor device according to claim 5, wherein the first trenches adjacent to one another are coupled by blocking trenches extending in the first direction.

7. The semiconductor device according to claim 6, wherein the blocking trenches are formed in the inactive cell forming area and the sense cell forming area.

8. The semiconductor device according to claim 7, wherein the blocking trenches are formed so as to differ in forming position for every said first trenches adjacent to each other.

9. The semiconductor device according to claim 7, wherein the blocking trenches extend in alignment in the first direction so as to intersect with the first trenches extending in the second direction side by side in the first direction.

10. The semiconductor device according to claim 7, wherein the blocking trenches have the same structure as the first trenches.

11. The semiconductor device according to claim 1,

wherein an active cell forming area formed with the active cell, a sense cell forming area formed with the sense cell, and an inactive cell forming area formed with the inactive cell exist in the semiconductor substrate,

wherein the sense cell forming area is formed in a region in which its periphery is surrounded by the active cell forming area, and

wherein the inactive cell forming area is formed between the sense cell forming area and the active cell forming area.

12. The semiconductor device according to claim 11, further including a source pad electrically coupled to the source region of the active cell, and a sense pad electrically coupled to the source region of the sense cell,

wherein electrical coupling between the source region of the active cell and the source pad is performed by a plug coupled to the source region of the active cell from an interlayer insulating film formed over the active cell, and a first wiring coupled to the plug and formed over the interlayer insulating film, and

wherein electrical coupling between the source region of the sense cell and the sense pad is performed by a plug coupled to the source region of the sense cell from the interlayer insulating film formed over the sense cell, and a second wiring coupled to the plug and formed in a layer above the first wiring.

13. The semiconductor device according to claim 1,

wherein an active cell forming area formed with the active cell, a sense cell forming area formed with the sense cell, and an inactive cell forming area formed with the inactive cell exist in the semiconductor substrate,

wherein the sense cell forming area has a region in which at least part thereof is not surrounded by the active cell forming area, and

wherein the inactive cell forming area is formed between the sense cell forming area and the active cell forming area.

14. The semiconductor device according to claim 13, further including a source pad electrically coupled to the source region of the active cell, and a sense pad electrically coupled to the source region of the sense cell,

wherein electrical coupling between the source region of the active cell and the source pad is performed by a plug coupled to the source region of the active cell from an interlayer insulating film formed over the active cell, and a first wiring coupled to the plug and formed over the interlayer insulating film,

wherein electrical coupling between the source region of the sense cell and the sense pad is performed by a plug coupled to the source region of the sense cell from the interlayer insulating film formed over the sense cell, and a third wiring of the same layer as the first wiring coupled to the plug, and

wherein the third wiring is drawn from a region unsurrounded by the active cell forming area and coupled to the sense pad.

15. The semiconductor device according to claim 1, wherein a third semiconductor region of the second conduction type is formed in a lower portion of each of the trenches respectively formed in the active cell, the sense cell and the inactive cell.

16. The semiconductor device according to claim 15, wherein the third semiconductor region is in contact with the semiconductor substrate.

17. The semiconductor device according to claim 1, wherein an electric field relaxation layer is formed between the active cell forming area formed with the active cell and the inactive cell forming area formed with the inactive cell.

18. The semiconductor device according to claim 17, wherein the electric field relaxation layer is formed of a fourth semiconductor region of the second conduction type.

19. A semiconductor device comprising:

(a) an active cell which causes a load current to flow therethrough;

(b) a sense cell which detects a magnitude of the load current flowing through the active cell; and

(c) a inactive cell which separates the active cell and the sense cell from each other,

wherein each of the active cell, the sense cell and the inactive cell includes;

(d1) a first semiconductor region of a first conduction type formed over a first surface of a semiconductor substrate corresponding to the first conduction type;

(d2) a second semiconductor region of a second conduction type corresponding to a conduction type opposite to the first conduction type, said second semiconductor region being formed over the first semiconductor region;

(d3) a trench which penetrates the second semiconductor region to reach the first semiconductor region and is formed so as not to reach the semiconductor substrate;

(d4) a gate insulating film formed in a bottom face of the trench and a side surface thereof;

(d5) a gate electrode formed so as to bury the trench via the gate insulating film; and

(d6) a drain region comprising the semiconductor substrate corresponding to the first conduction type,

wherein (d7) each of the active cell and the sense cell further has a source region formed in alignment with the trench and comprising a semiconductor region of the first conduction type formed over the second semiconductor region, whereas the inactive cell does not include the source region, and

wherein a third semiconductor region of the second conduction type is formed in a lower portion of each of the trenches respectively formed in the active cell, the sense cell and the inactive cell.

20. The semiconductor device according to claim 19, wherein the third semiconductor region is in contact with the semiconductor substrate.

21. A method for forming a semiconductor device in which an active cell which causes a load current to flow therethrough, a sense cell which detects a magnitude of the load current flowing through the active cell, and an inactive cell which separates the active cell and the sense cell from each other, are formed in a semiconductor substrate, said method comprising the steps of:

(a) forming a first semiconductor region of a first conduction type over a first surface of the semiconductor substrate corresponding to the first conduction type;

(b) forming a trench having a depth unextended to the semiconductor substrate in the first semiconductor region;

(c) forming a third semiconductor region of a second conduction type corresponding to a conduction type opposite to the first conduction type in a lower portion of the trench;

(d) forming a first insulating film over a bottom face of the trench and a side surface thereof;

(e) forming a dummy gate electrode inside the trench via the first insulating film;

(f) eliminating part of the first insulating film formed over the side surface of the trench;

(g) forming a second insulating film over the dummy gate electrode and eliminating part of the first insulating film thereby to form a gate insulating film in the side surface of the trench exposed;

(h) forming a gate electrode over the dummy gate electrode via the second insulating film interposed therebetween and inside the trench; and

(i) introducing an impurity of the second conduction type within the first semiconductor region thereby to form a second semiconductor region,

wherein after the (i) step, a source region comprising a semiconductor region of the first conduction type is formed in a region lying within the second semiconductor region and aligned with the trench in each of an active cell forming area for forming the active cell and a sense cell forming area for forming the sense cell, and the source region is not formed in an inactive cell forming area for forming the inactive cell.

22. The method according to claim 21, wherein the third semiconductor region formed in the (c) step is in contact with the semiconductor substrate.