POWER MOS TRANSISTOR DEVICE AND LAYOUT

• US 20090189220A1
• Filed: 05/19/2008
• Published: 07/30/2009
• Est. Priority Date: 01/30/2008
• Status: Active Grant

• Current Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Original Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Inventors: Lee, Hsin-Ming, Chang, Chih-Heng
• Granted Patent: US 7,948,032 B2
• Time in Patent Office: Days
• US Class Current: 257/337
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

A power metal-oxide semiconductor (MOS) transistor device is provided. The power MOS transistor device includes a drain region disposed in a substrate, a gate structure layer disposed over the substrate, and enclosing a periphery of the drain region, and a source region formed in the substrate and distributed at an outer periphery of the gate structure layer. In addition, the MOS transistor device can, for example, form a transistor array.

Claims

1. A power metal-oxide semiconductor (MOS) transistor device, comprising:

a drain region, disposed in a substrate;

a gate structure layer, disposed on the substrate, and enclosing a periphery of the drain region; and

a source region, disposed in the substrate, and distributed at an outer periphery of the gate structure layer.

2. The power MOS transistor device as claimed in claim 1, wherein the gate structure layer includes a stacked gate dielectric layer and a gate layer.

3. The power MOS transistor device as claimed in claim 1, wherein the source region continuously or discontinuously encloses the gate structure layer.

4. The power MOS transistor device as claimed in claim 3 further comprising a base region disposed adjacent to the source region and located at a periphery of the source region.

5. The power MOS transistor device as claimed in claim 4, wherein the base region is shared by an adjacent power MOS device.

6. A power MOS transistor structure, comprising:

a first transistor device, comprising;

a first drain region, disposed in a substrate;

a first gate structure layer, disposed on the substrate, and enclosing a periphery of the first drain region; and

a first source region, disposed in the substrate, and distributed at an outer periphery of the first gate structure layer; and

a second transistor device, disposed adjacent to the first transistor device, and the second transistor device comprising;

a second drain region, disposed in the substrate;

a second gate structure layer, disposed on the substrate, and enclosing a periphery of the second drain region; and

a second source region, disposed in the substrate, and distributed at an outer periphery of the second gate structure layer.

7. The power MOS transistor structure as claimed in claim 6, wherein the first gate structure layer and the second gate structure layer respectively comprise a staked gate dielectric layer and a gate layer.

8. The power MOS transistor structure as claimed in claim 6, wherein the first source region continuously or discontinuously encloses an outer periphery of the first gate structure layer.

9. The power MOS transistor structure as claimed in claim 8, further comprising:

a base region, disposed adjacent to the first source region and the second source region, and located at a periphery of the first and the second source regions.

10. The power MOS transistor structure as claimed in claim 9, wherein the first transistor device and the second transistor device share the base region.

11. The power MOS transistor structure as claimed in claim 6, wherein the first gate structure layer and the second gate structure layer are connected.

12. The power MOS transistor structure as claimed in claim 11, wherein a joint of the first gate structure layer and the second gate structure layer has at least a contact structure.

13. The power MOS transistor structure as claimed in claim 6, wherein shapes of the drain regions are regular quadrangles.

14. The power MOS transistor structure as claimed in claim 6, wherein shapes of the drain regions are rectangles.

15. A layout of a power MOS transistor, comprising:

a plurality of transistor units, forming a transistor array, wherein the transistor array comprises at least;

a first transistor device, comprising;

a first drain region, disposed in a substrate;

a first gate structure layer, disposed on the substrate, and enclosing a periphery of the drain region; and

a first source region, disposed in the substrate, and distributed at an outer periphery of the first gate structure layer; and

a second transistor device, disposed adjacent to the first transistor device, and the second transistor device comprising;

a second drain region, disposed in the substrate;

a second gate structure layer, disposed on the substrate, and enclosing a periphery of the second drain region; and

a second source region, disposed in the substrate, and distributed at an outer periphery of the second gate structure layer.

16. The layout of a power MOS transistor as claimed in claim 15, wherein the first gate structure layer and the second gate structure layer respectively comprise a staked gate dielectric layer and a gate layer.

17. The layout of a power MOS transistor as claimed in claim 15, wherein the first source region continuously or discontinuously encloses an outer periphery of the first gate structure layer.

18. The layout of a power MOS transistor as claimed in claim 17 further comprising:

a base region, disposed adjacent to the first source region and the second source region, and located at a periphery of the first and the second source regions.

19. The layout of a power MOS transistor as claimed in claim 18, wherein the first transistor device and the second transistor device share the base region.

20. The layout of a power MOS transistor as claimed in claim 15, wherein the first gate structure layer and the second gate structure layer are connected.

21. The layout of a power MOS transistor as claimed in claim 15, wherein a joint of the first gate structure layer and the second gate structure layer has at least a contact structure.

22. The layout of a power MOS transistor as claimed in claim 15, wherein shapes of the drain regions are quadrangles.

23. The layout of a power MOS transistor as claimed in claim 15, wherein shapes of the drain regions are rectangles.