METHOD OF FORMING TRENCH ISOLATION STRUCTURES AND SEMICONDUCTOR DEVICE PRODUCED THEREBY

• US 20090189246A1
• Filed: 07/23/2008
• Published: 07/30/2009
• Est. Priority Date: 01/30/2008
• Status: Abandoned Application

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: ProMOS Technologies, Inc.
• Inventors: WU, Hsiao-Che, TSAI, Wen-Li, LI, Ming-Yen
• Application Number:
  US12/178,154
• Publication Number:
  US 20090189246A1
• Time in Patent Office: Days
• US Class Current: 257/510
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264

Abstract

A method for forming a trench isolation structure and a semiconductor device are provided. The method comprises the following steps: forming a patterned mask on a semiconductor substrate; defining a trench with a predetermined depth D by using the patterned mask, wherein the trench has a bottom and a side wall; forming a liner layer covering the bottom and the side wall of the trench; substantially filling the trench with a flowable oxide from the bottom to a thickness d1 to form an oxide layer; forming a barrier layer with a thickness d′ to cover and completely seal the surface of the oxide layer, wherein d′<d1 and d1+d′≦1/2D; forming an insulating layer to fill the trench; and conducting a planarization process wherein the patterned mask is used as a stop layer. In the semiconductor substrate, the oxide layer, essentially composed of the flowable oxide, is confined in an isolated region. As a result, the quality of the semiconductor device manufactured by the subsequent processes on the substrate due to the diffusion of the dopants contained in the oxide layer will remain unaffected.

Claims

1. A method for forming a trench isolation structure comprising:

forming a patterned mask on a semiconductor substrate;

defining a trench with a predetermined depth D by using the patterned mask, wherein the trench has a bottom and a side wall;

forming a liner layer covering the bottom and the side wall of the trench;

substantially filling the trench with a flowable oxide from the bottom to a thickness d1 to form an oxide layer;

forming a barrier layer with a thickness d′

to cover the surface of the oxide layer and completely seal the oxide layer, wherein d′

<

d1 and d1+d′

≦

1/2D;

forming an insulating layer to fill the trench; and

conducting a planarization process wherein the patterned mask is used as a stop layer.

2. The method of claim 1, further comprising an annealing step before forming the barrier layer.

3. The method of claim 1, wherein the liner layer comprises a silicon nitride layer.

4. The method of claim 1, wherein the flowable oxide is boron phosphorus silicon glass (BPSG).

5. The method of claim 2, wherein the annealing step is conducted at a temperature ranging from about 800°

C. to about 1200°

C.

6. The method of claim 1, wherein the barrier layer is a silicon nitride layer.

7. The method of claim 1, wherein the thickness d′

of the barrier layer is about 2 nm to about 10 nm.

8. A semiconductor device comprising:

a semiconductor substrate; and

a plurality of isolation trenches located in the semiconductor substrate, wherein each trench has a depth D much greater than its diameter and a liner layer covering an inside of the trench, and the material filled in the trench comprises;

an oxide layer, with a thickness d1, essentially composed of a flowable oxide and disposed on the liner layer on the bottom of the trench to substantially fill the bottom;

a barrier layer with a thickness d′

disposed on the oxide layer to completely seal the oxide layer, wherein d′

<

d1 and d1+d′

≦

1/2D; and

an insulating layer which is disposed on the barrier layer and fills the trench.

9. The device of claim 8, wherein the liner layer comprises a silicon nitride layer.

10. The device of claim 8, wherein the oxide layer is boron phosphorus silicon glass (BPSG).

11. The device of claim 8, wherein the barrier layer is a silicon nitride layer.

12. The device of claim 8, wherein the thickness d′

of the barrier layer is about 2 nm to about 10 nm.

13. The device of claim 8, wherein the liner layer is a continuous layer.

14. The device of claim 8, wherein the liner layer has a thickness ranging from about 10 nm to about 40 nm.