Methods And Apparatus For Planar Extension Of Electrical Conductors Beyond The Edges Of A Substrate

• US 20090189627A1
• Filed: 12/01/2008
• Published: 07/30/2009
• Est. Priority Date: 07/07/2006
• Status: Active Grant

• Current Assignee: Translarity, Inc.
• Original Assignee: Advanced Inquiry Systems, Inc.
• Inventors: Johnson, Morgan T.
• Granted Patent: US 7,724,008 B2
• Time in Patent Office: Days
• US Class Current: 324/762.50
• CPC Class Codes: G01R 1/07342 the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06

Abstract

Concurrent electrical access to the pads of integrated circuits on a wafer is provided by an edge-extended wafer translator that carries signals from one or more pads on one or more integrated circuits to contact terminals on the inquiry-side of the edge-extended wafer translator, including portions of the inquiry-side that are superjacent the wafer when the wafer and the edge-extended wafer translator are in a removably attached state, and portions of the inquiry side that reside outside a region defined by the intersection of the wafer and the edge-extended wafer translator. In a further aspect of the present invention, access to the pads of integrated circuits on a wafer is additionally provided by contact terminals in a second inquiry area located on the wafer-side of the edge-extended wafer translator in a region thereof bounded by its outer circumference and the circumference of the attached wafer.

Claims

1. A method of providing electrical access to one or more pads of one or more integrated circuits on a wafer, comprising:

providing an edge-extended wafer translator having a wafer-side and an inquiry-side, a first plurality of contact terminals disposed on a first portion of the wafer-side, a second plurality of contact terminals disposed on a second portion of the wafer-side, a third plurality of contact terminals disposed on a first portion of the inquiry-side, and a fourth plurality of contact terminals disposed on a second portion the inquiry-side;

aligning the wafer and the edge-extended wafer translator to each other; and

removably attaching the aligned wafer and edge-extended wafer translator such that the first plurality of contact terminals are in electrical contact with the one or more pads of the one or more integrated circuits;

wherein the second portion of the wafer-side is an area outside the region where the wafer is removably attached to the edge-extended wafer translator, and wherein the first plurality of contact terminals and the second plurality of contact terminals have different contact areas and different spacing therebetween.

2. The method of claim 1, wherein each of the second plurality of contact terminals is electrically coupled to corresponding ones of the first plurality of contact terminals through wire paths internal to the edge-extended wafer translator.

3. The method of claim 2, wherein each of the third plurality of contact terminals is electrically coupled to corresponding ones of the first plurality of contact terminals through wire paths internal to the edge-extended wafer translator.

4. The method of claim 3, wherein each of the fourth plurality of contact terminals is electrically coupled to corresponding ones of the first plurality of contact terminals through wire paths internal to the edge-extended wafer translator.

5. The method of claim 4, further comprising removably attaching a wafer to the wafer-side of the edge-extended wafer translator by a pressure differential.