SCHMITT-TRIGGER-BASED LEVEL DETECTION CIRCUIT

• US 20090189665A1
• Filed: 01/22/2009
• Published: 07/30/2009
• Est. Priority Date: 01/28/2008
• Status: Active Grant

• Current Assignee: Faraday Technology Corp.
• Original Assignee: Faraday Technology Corp.
• Inventors: CHEN, SHENG-HUA, WU, JENG-HUANG
• Granted Patent: US 7,764,101 B2
• Time in Patent Office: Days
• US Class Current: 327/206
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger
• CPC Class Codes: H03K 5/082 with an adaptive threshold

Abstract

A Schmitt trigger includes A first PMOS transistors having the drains and sources thereof serially connected and coupled between a voltage source and an output end, and having gates thereof coupled to an input end; B first NMOS transistors having the drains and sources thereof serially connected and coupled between the output end and ground, and having gates thereof coupled to the input end; C second PMOS transistors, each being coupled between ground and a node between the drain and the source of the first PMOS transistors and having the gate thereof coupled to the output end; and D second NMOS transistors, each being coupled between the voltage source and a node between the drain and the source of the first NMOS transistors and having the gate thereof coupled to the output end. A is greater than 2 and C, and B is greater than 2 and D.

Claims

1. A Schmitt trigger, comprising:

a number A of first PMOS transistors having the drains and sources thereof serially connected and coupled between a voltage source and an output end, and having gates thereof coupled to an input end;

a number B of first NMOS transistors having the drains and sources thereof serially connected and coupled between the output end and ground, and having gates thereof coupled to the input end;

a number C of second PMOS transistors functioning as feedback transistors, each of which is coupled between ground and a node between the drain and the source of the first PMOS transistors and has the gate thereof coupled to the output end; and

a number D of second NMOS transistors functioning as feedback transistors, each of which is coupled between the voltage source and a node between the drain and the source of the first NMOS transistors and has the gate thereof coupled to the output end;

wherein A is greater than 2 and greater than C, and B is greater than 2 and greater than D.

2. The use of the Schmitt trigger according to claim 1 in a level detection circuit of a power-detecting module.

3. A Schmitt trigger, comprising:

a number A of first PMOS transistors having the drains and sources thereof serially connected and coupled between a voltage source and an output end, and having gates thereof coupled to an input end;

a number B of first NMOS transistors having the drains and sources thereof serially connected and coupled between the output end and ground, and having gates thereof coupled to the input end;

a number C of second PMOS transistors functioning as feedback transistors, each of which is coupled to a node between the drain and the source of the first PMOS transistors and has the gate thereof coupled to the output end;

a number D of second NMOS transistors functioning as feedback transistors, each of which is coupled to a node between the drain and the source of the first NMOS transistors and has the gate thereof coupled to the output end; and

a switch control unit coupled to the drains of the second PMOS transistors for selectively connecting the drains of the second PMOS transistors to ground;

wherein A is greater than 2 and greater than C, and B is greater than 2 and greater than D.

4. The use of the Schmitt trigger according to claim 3 in a level detection circuit of a power-detecting module.

5. The Schmitt trigger according to claim 3 wherein the switch control unit is further coupled to the drains of the second NMOS transistors for selectively connecting the drains of the second NMOS transistors to the voltage source.

6. The Schmitt trigger according to claim 5 wherein the switch control unit includes:

a number C of first switches corresponding to the number C of second PMOS transistors, respectively, each of which is coupled between the ground and the drain of the corresponding second PMOS transistor and selectively connects the drain of the corresponding second PMOS transistor to ground according to a signal at a control end thereof; and

a number D of second switches corresponding to the number D of second NMOS transistors, respectively, each of which is coupled between the voltage source and the drain of the corresponding second NMOS transistor and selectively connects the drain of the corresponding second NMOS transistor to the voltage source according to a signal at a control end thereof.

7. A Schmitt trigger, comprising:

a number A of first PMOS transistors having the drains and sources thereof serially connected and coupled between a voltage source and an output end, and having gates thereof coupled to an input end;

a number B of first NMOS transistors having the drains and sources thereof serially connected and coupled between the output end and ground, and having gates thereof coupled to the input end;

a number C of second PMOS transistors functioning as feedback transistors, each of which is coupled to a node between the drain and the source of the first PMOS transistors and has the gate thereof coupled to the output end;

a number D of second NMOS transistors functioning as feedback transistors, each of which is coupled to a node between the drain and the source of the first NMOS transistors and has the gate thereof coupled to the output end; and

a switch control unit coupled to the drains of the second NMOS transistors for selectively connecting the drains of the second NMOS transistors to the voltage source.

wherein A is greater than 2 and greater than C, and B is greater than 2 and greater than D.

8. The Schmitt trigger according to claim 7 wherein the switch control unit is further coupled to the drains of the second PMOS transistors for selectively connecting the drains of the second PMOS transistors to ground.

9. The Schmitt trigger according to claim 8 wherein the switch control unit includes:

a number C of first switches corresponding to the number C of second PMOS transistors, respectively, each of which is coupled between the ground and the drain of the corresponding second PMOS transistor and selectively connects the drain of the corresponding second PMOS transistor to ground according to a signal at a control end thereof; and

a number D of second switches corresponding to the number D of second NMOS transistors, respectively, each of which is coupled between the voltage source and the drain of the corresponding second NMOS transistor and selectively connects the drain of the corresponding second NMOS transistor to the voltage source according to a signal at a control end thereof.

10. The use of the Schmitt trigger according to claim 7 in a level detection circuit of a power-detecting module.