HYBRID CONTENT ADDRESSABLE MEMORY

• US 20090190386A1
• Filed: 04/09/2009
• Published: 07/30/2009
• Est. Priority Date: 03/26/2004
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: KIM, Jin Ki
• Granted Patent: US 8,031,502 B2
• Time in Patent Office: Days
• US Class Current: 365/49.17
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A CAM device memory array having different types of memory cells is disclosed. A CAM device memory array is subdivided into at least two different portions, where each portion uses only one particular type of CAM cell, and each portion is dedicated to storing a particular type of data. In particular, at least one portion consists of binary CAM cells and the other portion consists of ternary CAM cells. The portions can be partitioned along the row, or matchline, direction or along the bitline direction. Since particular data formats only require predefined bit positions of a word of data to be ternary in value, the remaining binary bit positions can be stored in binary CAM cells. Therefore, the CAM device memory array will occupy an overall area that is less than memory arrays of the same density consisting exclusively of ternary CAM cells.

Claims

1. A content addressable memory device comprising:

rows of first matchlines precharged to a voltage level corresponding to a miss condition;

ternary cells connected in parallel to each of the first matchlines;

rows of second matchlines precharged to a voltage level corresponding to a miss condition;

binary cells connected in parallel to each of the second matchlines, the binary cells being smaller in size than the ternary cells and operable simultaneously with the ternary cells; and

searchlines connected to the ternary cells of the rows of first matchlines and to the binary cells of the rows of second matchlines.

2. The content addressable memory device of claim 1, further including matchline sense amplifiers connected to the first matchlines and the second matchlines for detecting one of the miss condition and a match condition in response to search data on the searchlines, each matchline sense amplifier providing a match output if data stored in the ternary cells and the binary cells of each row matches the search data.

3. The content addressable memory device of claim 1, wherein the rows of first matchlines are interleaved with the rows of second matchlines.

4. The content addressable memory device of claim 1, wherein one row of the rows of first matchlines is adjacent to at least two consecutive rows of second matchlines.

5. The content addressable memory device of claim 1, wherein the ternary cells include static random access memory (SRAM) based ternary content addressable memory cells.

6. The content addressable memory device of claim 1, wherein the binary cells include static random access memory (SRAM) based binary content addressable memory cells.

7. The content addressable memory device of claim 1, wherein the ternary cells include dynamic random access memory (DRAM) based ternary content addressable memory cells.

8. The content addressable memory device of claim 1, wherein the binary cells include dynamic random access memory (DRAM) based binary content addressable memory cells.

9. A content addressable memory (CAM) device comprising:

a first matchline row prechargeable to a first voltage level corresponding to a first miss condition;

a second matchline row prechargeable to a second voltage level corresponding to a second miss condition;

a ternary CAM cell coupled to the first matchline;

a binary CAM cell coupled to the second matchline, the binary CAM cell being smaller than the ternary CAM cell and the binary CAM cell being simultaneously operable with the ternary CAM cell; and

the ternary CAM cell and the binary CAM cell being coupled to a common bitline and searchline.

10. The CAM device as claimed in claim 9, wherein the ternary CAM cell comprises a static random access memory (SRAM) based ternary CAM cell.

11. The CAM device as claimed in claim 9, wherein the binary CAM cell comprises a static random access memory (SRAM) based binary CAM cell.

12. The CAM device as claimed in claim 9, wherein the ternary CAM cell comprises a dynamic random access memory (DRAM) based ternary CAM cell.

13. The CAM device as claimed in claim 9, further comprising:

a first sense circuit coupled to the first matchline row for detecting one of the first miss condition or a first match condition on the first matchline row; and

a second sense circuit coupled to the second matchline row for detecting one of the second miss condition or a second match condition on the second matchline row.

14. The CAM device as claimed in claim 13, wherein a result provided by the first sense circuit is maskable.

15. The CAM device as claimed in claim 13, wherein a result provided by the second sense circuit is maskable.

16. The CAM device as claimed in claim 9, wherein the first voltage level and the second voltage level are substantially the same.

17. The CAM device as claimed in claim 13, wherein the first match condition and the second match condition correspond to substantially a same voltage of the first matchline and the second matchline.