Integrated SRAM and FLOTOX EEPROM memory device

• US 20090190402A1
• Filed: 01/05/2009
• Published: 07/30/2009
• Est. Priority Date: 01/03/2008
• Status: Active Grant

• Current Assignee: Aplus Flash Technology, Inc.
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Lee, Peter Wung, Hsu, Fu-Chang
• Granted Patent: US 8,331,150 B2
• Time in Patent Office: Days
• US Class Current: 365/185.08
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

A nonvolatile SRAM circuit has an SRAM cell and one or two FLOTOX EEPROM cells connected to the data storage terminals of the SRAM cell. In programming to a first data level, the threshold voltage of a FLOTOX EEPROM transistor is brought to a programmed voltage level greater than a read voltage level and erasing to a second data level, the threshold voltage of the FLOTOX EEPROM transistor is brought to an erased voltage level less than the read voltage level. The nonvolatile SRAM array provides for restoring data to an SRAM cell from a FLOTOX EEPROM memory cell(s) at a power initiation and storing data to the FLOTOX EEPROM memory cell(s) to the SRAM cell at power termination. A power detection circuit for providing signals indicating power initiation and power termination to instigate restoration and storing of data between an SRAM cell and a FLOTOX EEPROM cell(s).

Claims

1. An integrated nonvolatile static random access memory circuit formed on a substrate, the integrated nonvolatile static random access memory circuit comprising:

a static random access memory cell comprising;

a latched memory element to retain a digital signal indicative of a data bit at a first data terminal and a complementary digital signal indicative of a complementary data bit a second data terminal, and

a first access transistor connected to allow control access of a bit line and a second access transistor connected to allow control access of a complementary bit line to the latched memory element for writing and reading the digital signal to and from the latched memory element, the first and second access transistors having control gates in communication with an SRAM word line for controlling access of the latched memory element to the first and second bit lines; and

a first floating gate tunnel oxide (FLOTOX) EEPROM element in communication with the latched memory element through the first data terminal to receive and permanently retain the digital signal from the latched memory element;

wherein the first floating gate tunnel oxide EEPROM element comprises;

a first floating gate tunnel oxide transistor including an EEPROM control gate connected to an EEPROM word line for controlling activation of the first floating gate tunnel oxide transistor and a floating gate for permanently retaining the digital signal,

a first select gating transistor having a drain connected to the first data terminal, a source connected to a drain of the floating gate tunnel oxide transistor, and a control gate connected to a first select gating signal for controlling access to the floating gate tunnel oxide transistor, and

a second select gating transistor having a drain connected to a source of the floating gate tunnel oxide transistor, a source connected to a source line, and a control gate connected to a second select gating signal for controlling access to the floating gate tunnel oxide transistor from the source line;

wherein programming to a first data level, the first floating gate tunnel oxide EEPROM element increases a threshold voltage of the first floating gate tunnel oxide transistor to a programmed voltage level greater than a read voltage level; and

wherein erasing to a second data level, the first floating gate tunnel oxide EEPROM element decreases the threshold voltage of the first floating gate tunnel oxide transistor to an erased voltage level less than the read voltage level.

2. The integrated nonvolatile static random access memory circuit of claim 1 further comprising:

a second floating gate tunnel oxide EEPROM element in communication with the latched memory element through the second data terminal to receive and permanently retain a complement of the digital signal from the latched memory element, wherein the second floating gate tunnel oxide EEPROM element comprises;

a second floating gate tunnel oxide transistor including a control gate to the EEPROM word line for controlling activation of the second floating gate tunnel oxide transistor and a floating gate for permanently retaining the complement of the digital signal,

a third select gating transistor having a source connected to a drain of the second floating gate tunnel oxide transistor, a drain connected to the second data terminal, and a control gate connected to a first select gating signal for controlling access to the second floating gate tunnel oxide transistor, and

a fourth select gating transistor having a drain connected to a source of the second floating gate tunnel oxide transistor, a source connected to the source line, and a control gate connected to the second select gating signal for controlling access to the second floating gate tunnel oxide transistor from the source line;

wherein programming to the first data level, the second floating gate tunnel oxide EEPROM element increases the threshold voltage of the second floating gate tunnel oxide transistor to the programmed voltage level greater than a read voltage level; and

wherein erasing to a second data level, the second floating gate tunnel oxide EEPROM element decreases the threshold voltage of the second floating gate tunnel oxide transistor to the erased voltage level less than the read voltage level.

3. The integrated nonvolatile static random access memory circuit of claim 1 wherein the control gate of the first floating gate tunnel oxide transistor has a program signal that is from approximately +15V to approximately +20V applied to it to set the threshold voltage to the programmed voltage level that is greater than a read voltage level for programming and the source line of the first floating gate tunnel oxide transistor has an erase signal of from approximately +15V to approximately +20V applied to it to set the threshold voltage to the erased voltage level that is less than the read voltage level for erasing.

4. The integrated nonvolatile static random access memory circuit of claim 2 wherein the control gate of the first floating gate tunnel oxide EEPROM element or the second floating gate tunnel oxide EEPROM element has a program signal that is from approximately from approximately +15V to approximately +20V applied to it to set the threshold voltage to the programmed voltage level that is greater than a read voltage level for programming and the source line has an erase signal from approximately +15V to approximately +20V applied to it to set the threshold voltage to the erased voltage level that is less than the read voltage level.

5. The integrated nonvolatile static random access memory circuit of claim 1 wherein the first data terminal is connected to a storage node between the first access transistor and the latched memory element to transfer the digital signal to the first floating gate tunnel oxide EEPROM element.

6. The integrated nonvolatile static random access memory circuit of claim 2 wherein:

the first data terminal is connected to a storage node between the first access transistor and the latched memory element to transfer the digital signal to the first floating gate tunnel oxide EEPROM element; and

the second data terminal is connected to a complementary storage node between the second access transistor and the latched memory element to transfer the digital signal to the second floating gate tunnel oxide EEPROM element.

7. The integrated nonvolatile static random access memory circuit of claim 1 wherein:

the drain of the first floating gate tunnel oxide transistor is connected to the source of the first gating transistor such that when the first select gating signal is activated, the drain of the first floating gate tunnel oxide transistor is connected to the first data terminal of the latched memory element.

8. The integrated nonvolatile static random access memory circuit of claim 2 wherein:

the drain of the first floating gate tunnel oxide transistor is connected to the source of the first gating transistor of the first floating gate tunnel oxide EEPROM element such that when the first select gating signal is activated the drain of the first floating gate tunnel oxide transistor is connected to first data terminal of the latched memory element; and

the source of the second floating gate tunnel oxide transistor is connected to the drain of the first gating transistor of the second floating gate tunnel oxide EEPROM element such that when the first select gating signal is activated the drain of the second floating gate tunnel oxide transistor is connected to the second data terminal of the latched memory element.

9. The integrated nonvolatile static random access memory circuit of claim 1 wherein:

the control gate of the first floating gate tunnel oxide transistor is connected to the EEPROM word line to receive read, program, and erase signals.

10. The integrated nonvolatile static random access memory circuit of claim 2 wherein:

the control gates of the first and second floating gate tunnel oxide transistors are connected to the EEPROM word line to receive read, program, and erase signals.

11. The integrated nonvolatile static random access memory circuit of claim 1 wherein:

a source line signal is applied to the source line for reading, programming, and erasing the first floating gate tunnel oxide transistor.

12. The integrated nonvolatile static random access memory circuit of claim 2 wherein:

a source line signal is applied to the source line for reading, programming, and erasing the first and second floating gate tunnel oxide transistors.

13. The integrated nonvolatile static random access memory circuit of claim 7 wherein the static random access memory cell retains the digital signal as volatile digital data by setting the first select gating signal such that the first select gating transistors of the first floating gate tunnel oxide EEPROM element is deactivated and the static random access memory cell is isolated from the first floating gate tunnel oxide EEPROM elements.

14. The integrated nonvolatile static random access memory circuit of claim 8 wherein the static random access memory cell retains the digital signal as volatile digital data by setting the first select gating signal such that the first select gating transistors of the first and second floating gate tunnel oxide EEPROM elements are deactivated and the static random access memory cell is isolated from the first and second floating gate tunnel oxide EEPROM elements.

15. The integrated nonvolatile static random access memory circuit of claim 1 wherein at detection of a powering up of the integrated nonvolatile static random access memory circuit the digital signal retained in the first floating gate tunnel oxide transistor is restored to the static random access memory cell by reading the first floating gate tunnel oxide EEPROM element.

16. The integrated nonvolatile static random access memory circuit of claim 15 wherein the first floating gate tunnel oxide EEPROM element is read by the steps of:

setting the source line to a voltage level of a power supply voltage source;

setting the first and second select gating signals to a very large positive voltage level to activate the first and second select gating transistors;

setting the EEPROM word line to a read voltage level to activate the first floating gate tunnel oxide transistor if it is programmed with the data signal at a first data level and to remain inactive if the first floating gate tunnel oxide transistor is programmed with the data signal at a second data level such that if the first floating gate tunnel oxide transistor is activated the first data level is transferred to the static random access memory cell and if the first floating gate tunnel oxide transistor is not activated, the second data level is transferred to the static random access memory cell; and

setting the SRAM word line to a voltage level that will not turn on the first and second access transistors to prevent the static random access memory cell from being connected to the bit line and the complementary bit line.

17. The integrated nonvolatile static random access memory circuit of claim 15 wherein subsequent to restoring the digital signal to the static random access memory cell, the first floating gate tunnel oxide EEPROM element is erased.

18. The integrated nonvolatile static random access memory circuit of claim 17 wherein first floating gate tunnel oxide EEPROM element is erased the by the steps of:

setting the first select gating signal to a voltage level that will turn off the first select gating transistor to isolate the static random access memory cell from the first floating gate tunnel oxide EEPROM element;

setting the EEPROM word line to a ground reference voltage level;

setting the second select gating signal and the source line signal to the very large positive voltage level such that charge is extracted from the floating gate of the first floating gate tunnel oxide transistor; and

19. The integrated nonvolatile static random access memory circuit of claim 17 wherein subsequent to the erasing the first floating gate tunnel oxide EEPROM element, the first floating gate tunnel oxide EEPROM element is isolated from the static random access memory cell and the static random access memory cell is operated in a normal mode.

20. The integrated nonvolatile static random access memory circuit of claim 19 wherein at detection of a powering down of the integrated nonvolatile static random access memory circuit, the digital signal retained in the static random access memory cell is programmed to the first floating gate tunnel oxide transistor.

21. The integrated nonvolatile static random access memory circuit of claim 20 wherein the first floating gate tunnel oxide EEPROM element is programmed by the steps of:

setting the first select gating signal to the very high positive voltage level to activate the first select gating transistor;

setting the second select gating signal to turn off the first select gating transistor; and

setting the EEPROM word line to the very high positive voltage level such that if the data signal at the first data terminal is the first data level, charge is placed on the floating gate and if the data signal at the first data terminal is the second data level, charge is inhibited from entering the floating gate and the first floating gate tunnel oxide transistor remains erased.

22. The integrated nonvolatile static random access memory circuit of claim 2 wherein at detection of a powering up of the integrated nonvolatile static random access memory circuit the digital signal the complement digital signal retained in the first and second floating gate tunnel oxide transistors are restored to the static random access memory cell by reading the first and second floating gate tunnel oxide EEPROM elements.

23. The integrated nonvolatile static random access memory circuit of claim 22 wherein the first and second floating gate tunnel oxide EEPROM elements are read by the steps of:

setting the source line to a voltage level of a power supply voltage source;

setting the first and second select gating signals to a very large positive voltage level to activate the first and second select gating transistors of the first and second floating gate tunnel oxide EEPROM elements;

setting the EEPROM word line to a read voltage level to activate the first or second floating gate tunnel oxide transistors if it one is programmed with the data signal at a first data level and to remain inactive if the first or second floating gate tunnel oxide transistor is programmed with the data signal at a second data level such that if the first floating gate tunnel oxide transistor is activated and the second floating gate tunnel oxide transistor is deactivated, the first data level is transferred to the static random access memory cell and if the first floating gate tunnel oxide transistor is not activated and the second floating gate tunnel oxide transistors is activated, the second data level is transferred to the static random access memory cell; and

setting the SRAM word line to a voltage level that will not turn on the first and second access transistors to prevent the static random access memory cell from being connected to the bit line and the complementary bit line.

24. The integrated nonvolatile static random access memory circuit of claim 22 wherein subsequent to restoring the digital signal to the static random access memory cell, the first and second floating gate tunnel oxide EEPROM elements are erased.

25. The integrated nonvolatile static random access memory circuit of claim 24 wherein first and second floating gate tunnel oxide EEPROM elements are erased the by the steps of:

setting the first select gating signal to a voltage level that will turn off the first select gating transistor to isolate the static random access memory cell from the first and second floating gate tunnel oxide EEPROM elements;

setting the EEPROM word line to a ground reference voltage level; and

setting the second select gating signal and the source line signal to the very large positive voltage level such that charge is extracted from the floating gate of the first and second floating gate tunnel oxide transistors.

26. The integrated nonvolatile static random access memory circuit of claim 24 wherein subsequent to the erasing the first and second floating gate tunnel oxide EEPROM elements, the first and second floating gate tunnel oxide EEPROM elements are isolated from the static random access memory cell and the static random access memory cell is operated in a normal mode.

27. The integrated nonvolatile static random access memory circuit of claim 26 wherein at detection of a powering down of the integrated nonvolatile static random access memory circuit, the digital signal the complementary digital signal retained in the static random access memory cell are programmed to the first and second floating gate tunnel oxide transistors.

28. The integrated nonvolatile static random access memory circuit of claim 27 wherein the first and second floating gate tunnel oxide EEPROM transistors are programmed by the steps of:

setting the first select gating signal to the very high positive voltage level to activate the first select gating transistor;

setting the second select gating signal to turn off the first select gating transistor; and

setting the EEPROM word line to the very high positive voltage level such that if the data signal at the first data terminal is the first data level, charge is placed on the floating gate of the first floating gate tunnel oxide transistor and charge is inhibited from entering the floating gate of the second floating gate tunnel oxide transistor and if the first data terminal is at the second data level, charge is placed on the floating gate of the second floating gate tunnel oxide transistor and charge is inhibited from entering the floating gate of the first floating gate tunnel oxide transistor.

29. A nonvolatile static random access memory array comprising:

a plurality of integrated nonvolatile static random access memory circuits arranged in an array of rows and columns, each of the integrated nonvolatile static random access memory circuits comprising;

a static random access memory cell comprising;

a latched memory element to retain a digital signal indicative of a data bit at a first data terminal and a complementary digital signal indicative of a complementary data bit a second data terminal, and

a first access transistor connected to allow control access of a bit line and a second access transistor connected to allow control access of a complementary bit line to the latched memory element for writing and reading the digital signal to and from the latched memory element, the first and second access transistors having control gates in communication with an SRAM word line for controlling access of the latched memory element to the first and second bit lines; and

a first floating gate tunnel oxide (FLOTOX) EEPROM element in communication with the latched memory element through the first data terminal to receive and permanently retain the digital signal from the latched memory element;

wherein the first floating gate tunnel oxide EEPROM element comprises;

a first floating gate tunnel oxide transistor including an EEPROM control gate connected to an EEPROM word line for controlling activation of the first floating gate tunnel oxide transistor and a floating gate for permanently retaining the digital signal,

a first select gating transistor having a drain connected to the first data terminal, a source connected to a drain of the floating gate tunnel oxide transistor, and a control gate connected to a first select gating signal for controlling access to the floating gate tunnel oxide transistor, and

a second select gating transistor having a drain connected to a source of the floating gate tunnel oxide transistor, a source connected to a source line, and a control gate connected to a second select gating signal for controlling access to the floating gate tunnel oxide transistor from the source line;

wherein programming to a first data level, the first floating gate tunnel oxide EEPROM element increases a threshold voltage of the first floating gate tunnel oxide transistor to a programmed voltage level greater than a read voltage level; and

wherein erasing to a second data level, the first floating gate tunnel oxide EEPROM element decreases the threshold voltage of the first floating gate tunnel oxide transistor to an erased voltage level less than the read voltage level.

30. The nonvolatile static random access memory array of claim 29 wherein the each of the integrated nonvolatile static random access memory circuit further comprises:

a second floating gate tunnel oxide EEPROM element in communication with the latched memory element through the second data terminal to receive and permanently retain a complement of the digital signal from the latched memory element, wherein the second floating gate tunnel oxide EEPROM element comprises;

a second floating gate tunnel oxide transistor including a control gate connected to the EEPROM word line for controlling activation of the second floating gate tunnel oxide transistor and a floating gate for permanently retaining the complement of the digital signal,

a third select gating transistor having a drain connected to a drain of the second floating gate tunnel oxide transistor, a drain connected to the second data terminal, and a control gate connected to a first select gating signal for controlling access to the second floating gate tunnel oxide transistor, and

a fourth select gating transistor having a drain connected to a source of the second floating gate tunnel oxide transistor, a source connected to the source line, and a control gate connected to the second select gating signal for controlling access to the second floating gate tunnel oxide transistor from the source line;

wherein programming to the first data level, the second floating gate tunnel oxide EEPROM element increases the threshold voltage of the second floating gate tunnel oxide transistor to the programmed voltage level greater than a read voltage level; and

wherein erasing to a second data level, the second floating gate tunnel oxide EEPROM element decreases the threshold voltage of the second floating gate tunnel oxide transistor to the erased voltage level less than the read voltage level.

31. The nonvolatile static random access memory array of claim 29 wherein the EEPROM word line has a program signal that is from approximately +15V to approximately +20V to set the threshold voltage of a selected row of the first floating gate tunnel oxide transistors to the programmed voltage level that is greater than a read voltage level and the source line has an erase signal of from approximately +15V to approximately +20V to set the threshold voltage of a selected row of the first floating gate tunnel oxide transistors to the erased voltage level that is less than the read voltage level.

32. The nonvolatile static random access memory array of claim 30 wherein the EEPROM word line has a program signal that is from approximately +15V to approximately +20V to set the threshold voltage of a selected row of the first and second floating gate tunnel oxide transistors to the programmed voltage level that is greater than a read voltage level and the source line has an erase signal of from approximately +15V to approximately +20V to set the threshold voltage of a selected row of the first and second floating gate tunnel oxide transistors to the erased voltage level that is less than the read voltage level.

33. The nonvolatile static random access memory array of claim 29 further comprising a power detection circuit in communication with the plurality of integrated nonvolatile static random access memory circuits to detect a power interruption and a power initiation and communicate the detection of the power interruption and detection of the power initiation to the plurality of integrated nonvolatile static random access memory circuits.

34. The nonvolatile static random access memory array of claim 30 further comprising a power detection circuit in communication with the plurality of integrated nonvolatile static random access memory circuits to detect a power interruption and a power initiation and communicate the detection of the power interruption and detection of the power initiation to the plurality of integrated nonvolatile static random access memory circuits.

35. The nonvolatile static random access memory array of claim 29 wherein the first data terminal is connected to a storage node between the first access transistor and the latched memory element to transfer the digital signal to the first floating gate tunnel oxide EEPROM element.

36. The nonvolatile static random access memory array of claim 30 wherein:

the first data terminal is connected to a storage node between the first access transistor and the latched memory element to transfer the digital signal to the first floating gate tunnel oxide EEPROM element; and

the second data terminal is connected to a complementary storage node between the second access transistor and the latched memory element to transfer the digital signal to the second floating gate tunnel oxide EEPROM element.

37. The nonvolatile static random access memory array of claim 29 wherein:

the drain of the first floating gate tunnel oxide transistor is connected to the source of the first gating transistor such that when the first select gating signal is activated the drain of the first floating gate tunnel oxide transistor is connected to the first data terminal of the latched memory element.

38. The nonvolatile static random access memory array of claim 30 wherein:

the drain of the first floating gate tunnel oxide transistor is connected to the source of the first gating transistor of the first floating gate tunnel oxide EEPROM element such that when the first select gating signal is activated the drain of the first floating gate tunnel oxide transistor is connected to first data terminal of the latched memory element; and

the drain of the second floating gate tunnel oxide transistor is connected to the source of the first gating transistor of the second floating gate tunnel oxide EEPROM element such that when the first select gating signal is activated the drain of the second floating gate tunnel oxide transistor is connected to the second data terminal of the latched memory element.

39. The nonvolatile static random access memory array of claim 29 wherein:

the control gate of the first floating gate tunnel oxide transistor is connected to the EEPROM word line to receive read, program, and erase signals.

40. The nonvolatile static random access memory array of claim 30 wherein:

the control gates of the first and second floating gate tunnel oxide transistors is connected to the EEPROM word line receive read, program, and erase signals.

41. The nonvolatile static random access memory array of claim 29 wherein:

a source line signal is applied to the source line for reading, programming, and erasing the first floating gate tunnel oxide transistor.

42. The nonvolatile static random access memory array of claim 30 wherein:

a source line signal is applied to the source line for reading, programming, and erasing the first and second floating gate tunnel oxide transistors.

43. The nonvolatile static random access memory array of claim 35 wherein the static random access memory cell retains the digital signal as volatile digital data by setting the first select gating signal such that the first select gating transistors of the first floating gate tunnel oxide EEPROM element is deactivated and the static random access memory cell is isolated from the first floating gate tunnel oxide EEPROM elements.

44. The nonvolatile static random access memory array of claim 36 wherein the static random access memory cell retains the digital signal as volatile digital data by setting the first select gating signal such that the first select gating transistors of the first and second floating gate tunnel oxide EEPROM elements are deactivated and the static random access memory cell is isolated from the first and second floating gate tunnel oxide EEPROM elements.

45. The nonvolatile static random access memory array of claim 33 wherein when the power detection circuit detects the power initiation of the integrated nonvolatile static random access memory circuit the digital signal retained in the first floating gate tunnel oxide transistor is restored to the static random access memory cell by reading the first floating gate tunnel oxide EEPROM element.

46. The nonvolatile static random access memory array of claim 45 wherein the first floating gate tunnel oxide EEPROM element is read by the steps of:

setting the source line to a voltage level of a power supply voltage source;

setting the first and second select gating signals to a very large positive voltage level to activate the first and second select gating transistors;

setting the EEPROM word line to a read voltage level to activate the first floating gate tunnel oxide transistor if it is programmed with the data signal at a first data level and to remain inactive if the first floating gate tunnel oxide transistor is programmed with the data signal at a second data level such that if the first floating gate tunnel oxide transistor is activated the first data level is transferred to the static random access memory cell and if the first floating gate tunnel oxide transistor is not activated, the second data level is transferred to the static random access memory cell; and

setting the SRAM word line to a voltage level that will not turn on the first and second access transistors to prevent the static random access memory cell from being connected to the bit line and the complementary bit line.

47. The nonvolatile static random access memory array of claim 45 wherein subsequent to restoring the digital signal to the static random access memory cell, the first floating gate tunnel oxide EEPROM element is erased.

48. The nonvolatile static random access memory array of claim 47 wherein first floating gate tunnel oxide EEPROM element is erased the by the steps of:

setting the first select gating signal to a voltage level that will turn off the first select gating transistor to isolate the static random access memory cell from the first floating gate tunnel oxide EEPROM element;

setting the EEPROM word line to a ground reference voltage level;

setting the second select gating signal and the source line signal to the very large positive voltage level such that charge is extracted from the floating gate of the first floating gate tunnel oxide transistor; and

49. The nonvolatile static random access memory array of claim 47 wherein subsequent to the erasing the first floating gate tunnel oxide EEPROM element, the first floating gate tunnel oxide EEPROM element is isolated from the static random access memory cell and the static random access memory cell is operated in a normal mode.

50. The nonvolatile static random access memory array of claim 49 wherein when the power detection circuit detects a power interruption of the integrated nonvolatile static random access memory circuit, the digital signal retained in the static random access memory cell is programmed to the first floating gate tunnel oxide transistor.

51. The nonvolatile static random access memory array of claim 50 wherein the first floating gate tunnel oxide EEPROM element is programmed by the steps of:

setting the first select gating signal to the very high positive voltage level to activate the first select gating transistor;

setting the second select gating signal to turn off the first select gating transistor; and

setting the EEPROM word line to the very high positive voltage level such that if the data signal at the first data terminal is the first data level, charge is placed on the floating gate and if the data signal at the first data terminal is the second data level, charge is inhibited from entering the floating gate and the first floating gate tunnel oxide transistor remains erased.

52. The nonvolatile static random access memory array of claim 34 wherein the power detection circuit detects the power initiation of the integrated nonvolatile static random access memory circuit the digital signal the complement digital signal retained in the first and second floating gate tunnel oxide transistors are restored to the static random access memory cell by reading the first and second floating gate tunnel oxide EEPROM elements.

53. The nonvolatile static random access memory array of claim 52 wherein the first and second floating gate tunnel oxide EEPROM elements are read by the steps of:

setting the source line to a voltage level of a power supply voltage source;

setting the first and second select gating signals to a very large positive voltage level to activate the first and second select gating transistors of the first and second floating gate tunnel oxide EEPROM elements;

setting the EEPROM word line to a read voltage level to activate the first or second floating gate tunnel oxide transistors if it one is programmed with the data signal at a first data level and to remain inactive if the first or second floating gate tunnel oxide transistor is programmed with the data signal at a second data level such that if the first floating gate tunnel oxide transistor is activated and the second floating gate tunnel oxide transistor is deactivated, the first data level is transferred to the static random access memory cell and if the first floating gate tunnel oxide transistor is not activated and the second floating gate tunnel oxide transistors is activated, the second data level is transferred to the static random access memory cell; and

setting the SRAM word line to a voltage level that will not turn on the first and second access transistors to prevent the static random access memory cell from being connected to the bit line and the complementary bit line.

54. The nonvolatile static random access memory array of claim 52 wherein subsequent to restoring the digital signal to the static random access memory cell, the first and second floating gate tunnel oxide EEPROM elements are erased.

55. The nonvolatile static random access memory array of claim 54 wherein first and second floating gate tunnel oxide EEPROM elements are erased the by the steps of:

setting the first select gating signal to a voltage level that will turn off the first select gating transistor to isolate the static random access memory cell from the first and second floating gate tunnel oxide EEPROM elements;

setting the EEPROM word line to a ground reference voltage level; and

setting the second select gating signal and the source line signal to the very large positive voltage level such that charge is extracted from the floating gate of the first and second floating gate tunnel oxide transistors.

56. The nonvolatile static random access memory array of claim 54 wherein subsequent to the erasing the first and second floating gate tunnel oxide EEPROM elements, the first and second floating gate tunnel oxide EEPROM elements are isolated from the static random access memory cell and the static random access memory cell is operated in a normal mode.

57. The nonvolatile static random access memory array of claim 56 wherein the power detection circuit detects the power interruption of the integrated nonvolatile static random access memory circuit, the digital signal the complementary digital signal retained in the static random access memory cell are programmed to the first and second floating gate tunnel oxide transistors.

58. The nonvolatile static random access memory array of claim 57 wherein the first and second floating gate tunnel oxide EEPROM transistors are programmed by the steps of:

setting the first select gating signal to the very high positive voltage level to activate the first select gating transistor;

setting the second select gating signal to turn off the first select gating transistor; and

setting the EEPROM word line to the very high positive voltage level such that if the data signal at the first data terminal is the first data level, charge is placed on the floating gate of the first floating gate tunnel oxide transistor and charge is inhibited from entering the floating gate of the second floating gate tunnel oxide transistor and if the first data terminal is at the second data level, charge is placed on the floating gate of the second floating gate tunnel oxide transistor and charge is inhibited from entering the floating gate of the first floating gate tunnel oxide transistor.

59. A method for forming an integrated nonvolatile static random access memory comprises the steps of:

forming a plurality of integrated nonvolatile static random access memory circuits by the steps of;

forming a static random access memory cell for each of the integrated nonvolatile static random access memory circuits by the steps of;

forming a latched memory element to retain a digital signal indicative of a data bit at a first data terminal and a complementary digital signal indicative of a complementary data bit a second data terminal, and

forming a first access transistor connected to allow control access of a bit line and a second access transistor connected to allow control access of a complementary bit line to the latched memory element for writing and reading the digital signal to and from the latched memory element, the first and second access transistors having control gates in communication with an SRAM word line for controlling access of the latched memory element to the first and second bit lines; and

forming a first floating gate tunnel oxide EEPROM element for each of the integrated nonvolatile static random access memory circuits by the steps of;

forming a first floating gate tunnel oxide transistor including an EEPROM control gate connected to the EEPROM word line for controlling activation of the first floating gate tunnel oxide transistor and a floating gate for permanently retaining the digital signal,

forming a first select gating transistor having a drain connected to the first data terminal, a source connected to a drain of the first floating gate tunnel oxide transistor, and a control gate connected to a first select gating signal for controlling access to the floating gate tunnel oxide transistor, and

forming a second select gating transistor having a drain connected to a source of the first floating gate tunnel oxide transistor, a source connected to a source line, and a control gate connected to a second select gating signal for controlling access to the first floating gate tunnel oxide transistor from the source line;

connecting the first floating gate tunnel oxide EEPROM element to be in communication with the latched memory element through the first data terminal to receive and permanently retain the digital signal from the latched memory element;

arranging the plurality of integrated nonvolatile static random access memory circuits in an array of rows and columns,

programming selected first floating gate tunnel oxide EEPROM elements to a first data level by increasing a threshold voltage of the selected first floating gate tunnel oxide transistors to a programmed voltage level greater than a read voltage level; and

erasing selected first floating gate tunnel oxide EEPROM element to a second data level by decreasing the threshold voltage of the selected first floating gate tunnel oxide transistors to an erased voltage level less than the read voltage level.

60. The method for forming an integrated nonvolatile static random access memory of claim 59 wherein forming the each of the integrated nonvolatile static random access memory circuit further comprises the steps of:

forming a second floating gate tunnel oxide EEPROM element for each of the integrated nonvolatile static random access memory circuits by the steps of;

forming a second floating gate tunnel oxide transistor including an EEPROM control gate connected to the EEPROM word line for controlling activation of the second floating gate tunnel oxide transistor and a floating gate for permanently retaining the digital signal,

forming a third select gating transistor having a drain connected to the second data terminal, a source connected to a drain of the floating gate tunnel oxide transistor, and a control gate connected to a first select gating signal for controlling access to the second floating gate tunnel oxide transistor, and

forming a fourth select gating transistor having a drain connected to a source of the second floating gate tunnel oxide transistor, a source connected to a source line, and a control gate connected to a second select gating signal for controlling access to the floating gate tunnel oxide transistor from the source line;

connecting the second floating gate tunnel oxide EEPROM element to be in communication with the latched memory element through the second data terminal to receive and permanently retain the digital signal from the latched memory element;

programming selected second floating gate tunnel oxide EEPROM element to the first data level by increasing the threshold voltage of the selected second floating gate tunnel oxide transistors to the programmed voltage level greater than a read voltage level; and

erasing selected second floating gate tunnel oxide EEPROM elements to a second data level by decreasing the threshold voltage of the second selected floating gate tunnel oxide transistors to the erased voltage level less than the read voltage level.

61. The method for forming an integrated nonvolatile static random access memory of claim 59 wherein programming the first floating gate tunnel oxide EEPROM element comprises the steps of:

applying a program signal that is from approximately +15V to approximately +20V to the EEPROM word line to set the threshold voltage of a selected row of the first floating gate tunnel oxide transistors to the programmed voltage level that is greater than a read voltage level.

62. The method for forming an integrated nonvolatile static random access memory of claim 59 wherein erasing the first floating gate tunnel oxide EEPROM element comprises the steps of:

applying an erase signal of from approximately +15V to approximately +20V to the source line to set the threshold voltage of a selected row of the first floating gate tunnel oxide transistors to the erased voltage level that is less than the read voltage level.

63. The method for forming an integrated nonvolatile static random access memory of claim 60 wherein programming the first and second floating gate tunnel oxide EEPROM elements comprises the steps of:

applying a program signal that is from approximately +15V to approximately +20V to the EEPROM word line to set the threshold voltage of a selected row of the first floating gate tunnel oxide transistors to the programmed voltage level that is greater than a read voltage level.

64. The method for forming an integrated nonvolatile static random access memory of claim 60 wherein erasing the first and second floating gate tunnel oxide EEPROM element comprises the steps of:

applying an erase signal of from approximately +15V to approximately +20V to the source line to set the threshold voltage of a selected row of the first floating gate tunnel oxide transistors to the erased voltage level that is less than the read voltage level.

65. The method for forming an integrated nonvolatile static random access memory of claim 59 further comprising the steps of;

detecting a power initiation of the plurality of integrated nonvolatile static random access memory circuits;

detecting a power interruption of the plurality of integrated nonvolatile static random access memory circuits; and

communicating the detecting of the power interruption and detecting of the power initiation to the plurality of integrated nonvolatile static random access memory circuits.

66. The method for forming an integrated nonvolatile static random access memory of claim 60 further comprising the steps of;

detecting a power initiation of the plurality of integrated nonvolatile static random access memory circuits;

detecting a power interruption of the plurality of integrated nonvolatile static random access memory circuits; and

communicating the detecting of the power interruption and detecting of the power initiation to the plurality of integrated nonvolatile static random access memory circuits.

67. The method for forming an integrated nonvolatile static random access memory of claim 59 further comprising the step of connecting the first data terminal to a storage node between the first access transistor and the latched memory element to transfer the digital signal to the first floating gate tunnel oxide EEPROM element.

68. The method for forming an integrated nonvolatile static random access memory of claim 60 further comprising the step of:

connecting the first data terminal to a storage node between the first access transistor and the latched memory element to transfer the digital signal to the first floating gate tunnel oxide EEPROM element; and

connecting the second data terminal to a complementary storage node between the second access transistor and the latched memory element to transfer the digital signal to the second floating gate tunnel oxide EEPROM element.

69. The method for forming an integrated nonvolatile static random access memory of claim 59 forming the first floating gate tunnel oxide transistor comprises the step of:

connecting the drain of the first floating gate tunnel oxide transistor to the source of the first gating transistor such that when the first select gating signal is activated the drain of the first floating gate tunnel oxide transistor is connected to the first data terminal of the latched memory element.

70. The method for forming an integrated nonvolatile static random access memory of claim 60 wherein:

forming the first floating gate tunnel oxide transistor comprises the step of;

connecting the drain of the first floating gate tunnel oxide transistor to the source of the first gating transistor of the first floating gate tunnel oxide EEPROM element such that when the first select gating signal is activated the drain of the first floating gate tunnel oxide transistor is connected to first data terminal of the latched memory element; and

forming the second floating gate tunnel oxide transistor comprises the step of;

connecting the drain of the second floating gate tunnel oxide transistor to the source of the first gating transistor of the second floating gate tunnel oxide EEPROM element such that when the first select gating signal is activated the drain of the second floating gate tunnel oxide transistor is connected to the second data terminal of the latched memory element.

71. The method for forming an integrated nonvolatile static random access memory of claim 59 wherein forming the first floating gate tunnel oxide transistor comprises the step of connecting the control gate of the first floating gate tunnel oxide transistor to receive read, program, and erase signals.

72. The method for forming an integrated nonvolatile static random access memory of claim 60 wherein forming the first and second floating gate tunnel oxide transistor comprises the step of connecting the control gate of the first and second floating gate tunnel oxide transistor to receive read, program, and erase signals.

73. The method for forming an integrated nonvolatile static random access memory of claim 59 further comprises the step of applying a source line signal to the source line for reading, programming, and erasing the first floating gate tunnel oxide transistor.

74. The method for forming an integrated nonvolatile static random access memory of claim 60 further comprises the step of applying a source line signal to the source line for reading, programming, and erasing the first floating gate tunnel oxide transistor.

75. The method for forming an integrated nonvolatile static random access memory of claim 67 further comprises the step of setting the first select gating signal such that the first select gating transistors of the first floating gate tunnel oxide EEPROM element is deactivated and the static random access memory cell is isolated from the first floating gate tunnel oxide EEPROM elements so that the static random access memory cell retains the digital signal as volatile digital data.

76. The method for forming an integrated nonvolatile static random access memory of claim 68 further comprises the step of setting the first select gating signal such that the first select gating transistors of the first and second floating gate tunnel oxide EEPROM elements are deactivated and the static random access memory cell is isolated from the first and second floating gate tunnel oxide EEPROM elements so that the static random access memory cell retains the digital signal as volatile digital data.

77. The method for forming an integrated nonvolatile static random access memory of claim 65 further comprising:

restoring the digital signal retained in the first floating gate tunnel oxide transistor to the static random access memory cell by reading the first floating gate tunnel oxide EEPROM element upon detecting the power initiation of the integrated nonvolatile static random access memory circuit.

78. The method for forming an integrated nonvolatile static random access memory of claim 77 wherein reading the first floating gate tunnel oxide EEPROM element comprises the steps of:

setting the source line to a voltage level of a power supply voltage source;

setting the first and second select gating signals to a very large positive voltage level to activate the first and second select gating transistors;

setting the EEPROM word line to a read voltage level to activate the first floating gate tunnel oxide transistor if it is programmed with the data signal at a first data level and to remain inactive if the first floating gate tunnel oxide transistor is programmed with the data signal at a second data level such that if the first floating gate tunnel oxide transistor is activated the first data level is transferred to the static random access memory cell and if the first floating gate tunnel oxide transistor is not activated, the second data level is transferred to the static random access memory cell; and

setting the SRAM word line to a voltage level that will not turn on the first and second access transistors to prevent the static random access memory cell from being connected to the bit line and the complementary bit line.

79. The method for forming an integrated nonvolatile static random access memory of claim 77 further comprising the step of erasing the first floating gate tunnel oxide EEPROM element, subsequent to restoring the digital signal to the static random access memory cell,

80. The method for forming an integrated nonvolatile static random access memory of claim 79 wherein erasing the first floating gate tunnel oxide EEPROM comprises the steps of:

setting the first select gating signal to a voltage level that will turn off the first select gating transistor to isolate the static random access memory cell from the first floating gate tunnel oxide EEPROM element;

setting the EEPROM word line to a ground reference voltage level;

setting the second select gating signal and the source line signal to the very large positive voltage level such that charge is extracted from the floating gate of the first floating gate tunnel oxide transistor; and

81. The method for forming an integrated nonvolatile static random access memory of claim 79 further comprises the steps of:

isolating the first floating gate tunnel oxide EEPROM element from the static random access memory cell; and

operating the static random access memory cell in a normal mode, subsequent to the erasing the first floating gate tunnel oxide EEPROM element.

82. The method for forming an integrated nonvolatile static random access memory of claim 80 further comprising the steps of programming the digital signal retained in the static random access memory cell to the first floating gate tunnel oxide transistor detects the power interruption of the integrated nonvolatile static random access memory circuit.

83. The method for forming an integrated nonvolatile static random access memory of claim 82 wherein programming the first floating gate tunnel oxide EEPROM element comprises the steps of:

setting the first select gating signal to the very high positive voltage level to activate the first select gating transistor;

setting the second select gating signal to turn off the first select gating transistor; and

setting the EEPROM word line to the very high positive voltage level such that if the data signal at the first data terminal is the first data level, charge is placed on the floating gate and if the data signal at the first data terminal is the second data level, charge is inhibited from entering the floating gate and the first floating gate tunnel oxide transistor remains erased.

84. The method for forming an integrated nonvolatile static random access memory of claim 66 further comprising:

restoring the digital signal retained in the first and second floating gate tunnel oxide transistors to the static random access memory cell by reading the first and second floating gate tunnel oxide EEPROM elements upon detecting the power initiation of the integrated nonvolatile static random access memory circuit.

85. The method for forming an integrated nonvolatile static random access memory of claim 84 wherein the first and second floating gate tunnel oxide EEPROM elements are read by the steps of:

setting the source line to a voltage level of a power supply voltage source;

setting the first and second select gating signals to a very large positive voltage level to activate the first and second select gating transistors of the first and second floating gate tunnel oxide EEPROM elements;

setting the EEPROM word line to a read voltage level to activate the first or second floating gate tunnel oxide transistors if it one is programmed with the data signal at a first data level and to remain inactive if the first or second floating gate tunnel oxide transistor is programmed with the data signal at a second data level such that if the first floating gate tunnel oxide transistor is activated and the second floating gate tunnel oxide transistor is deactivated, the first data level is transferred to the static random access memory cell and if the first floating gate tunnel oxide transistor is not activated and the second floating gate tunnel oxide transistors is activated, the second data level is transferred to the static random access memory cell; and

setting the SRAM word line to a voltage level that will not turn on the first and second access transistors to prevent the static random access memory cell from being connected to the bit line and the complementary bit line.

86. The method for forming an integrated nonvolatile static random access memory of claim 84 wherein erasing the first and second floating gate tunnel oxide EEPROM elements is subsequent to restoring the digital signal to the static random access memory cell.

87. The method for forming an integrated nonvolatile static random access memory of claim 86 wherein erasing the first and second floating gate tunnel oxide EEPROM elements comprise the steps of:

setting the first select gating signal to a voltage level that will turn off the first select gating transistor to isolate the static random access memory cell from the first and second floating gate tunnel oxide EEPROM elements;

setting the EEPROM word line to a ground reference voltage level; and

setting the second select gating signal and the source line signal to the very large positive voltage level such that charge is extracted from the floating gate of the first and second floating gate tunnel oxide transistors.

88. The method for forming an integrated nonvolatile static random access memory of claim 86 further comprises the steps of:

isolating the first and second floating gate tunnel oxide EEPROM elements from the static random access memory cell; and

operating the static random access memory cell in a normal mode subsequent to the erasing the first and second floating gate tunnel oxide EEPROM elements.

89. The method for forming an integrated nonvolatile static random access memory of claim 88 wherein programming the digital signal the complementary digital signal retained in the static random access memory cell to the first and second floating gate tunnel oxide transistors occurs upon detecting the power interruption of the integrated nonvolatile static random access memory circuit.

90. The method for forming an integrated nonvolatile static random access memory of claim 89 wherein programming the first and second floating gate tunnel oxide EEPROM transistors comprises the steps of:

setting the first select gating signal to the very high positive voltage level to activate the first select gating transistor;

setting the second select gating signal to turn off the first select gating transistor; and

setting the EEPROM word line to the very high positive voltage level such that if the data signal at the first data terminal is the first data level, charge is placed on the floating gate of the first floating gate tunnel oxide transistor and charge is inhibited from entering the floating gate of the second floating gate tunnel oxide transistor and if the first data terminal is at the second data level, charge is placed on the floating gate of the second floating gate tunnel oxide transistor and charge is inhibited from entering the floating gate of the first floating gate tunnel oxide transistor.