NAND FLASH CONTENT ADDRESSABLE MEMORY

• US 20090190404A1
• Filed: 01/25/2008
• Published: 07/30/2009
• Est. Priority Date: 01/25/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Granted Patent: US 8,169,808 B2
• Time in Patent Office: Days
• US Class Current: 365/185.17
• CPC Class Codes: G11C 15/046 using non-volatile storage elements
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits

Abstract

NAND architecture non-volatile content addressable (CAM) memory devices and methods are described that allows for high density, low cost CAM devices. In addition, the NAND architecture non-volatile CAM memory operates with reduced power consumption characteristics for low power and portable applications. In one NAND architecture non-volatile CAM memory embodiment a wired NOR match line array is utilized. In another embodiment a NAND match line array is shown. In yet other embodiments, hierarchal addressing, hash addressing, tree search and algorithmic/hardware engine based search is detailed utilizing both conventional NAND architecture non-volatile Flash memory arrays and dedicated NAND architecture CAM arrays utilizing wired NOR and wired NAND match lines.

Claims

1. A NAND architecture content addressable memory (CAM) device, comprising:

a non-volatile memory array having a plurality of non-volatile memory cells arranged in a plurality of NAND architecture memory cell strings; and

a control circuit;

wherein the NAND architecture CAM memory device is adapted to search the non-volatile memory array for an input data word to locate a match.

2. The NAND architecture CAM memory device of claim 1, further comprising a search word register, wherein the search word register is adapted to store the input data word.

3. The NAND architecture CAM memory device of claim 1, wherein the non-volatile memory array is a non-volatile Flash memory array having a plurality of non-volatile memory cells arranged in rows and columns in a plurality of NAND architecture memory cell strings that are coupled through bit lines to sense amplifiers, where the control circuit is adapted to search the non-volatile Flash memory array for the input data word to locate a match by accessing a plurality of data words stored in the array and comparing them to the input data word.

4. The NAND architecture CAM memory device of claim 3, wherein the control circuit of the NAND architecture CAM memory device is adapted to pre-decode the input data word to select a section of the non-volatile Flash memory array to search for the input data word, where the pre-decoding is one of decoding all or some of the input data as a binary address, a hash algorithm decoding, a binary search tree, and sequential hierarchal table decoding.

5. The NAND architecture CAM memory device of claim 1, further comprising

a comparator coupled to a data cache to compare one or more data words sensed from the non-volatile Flash memory array to the input data word.

6. The NAND architecture CAM memory device of claim 1, further comprising:

an address decoder coupled to a plurality of word lines of the plurality of NAND memory cell strings;

a search word register having an inverting and non-inverting output for each bit position of a search word register, wherein each output of the search word register is coupled to a source-side connection of a NAND memory cell string of the plurality of NAND memory cell strings;

a match line coupled to a plurality of drain-side connections of the plurality of NAND memory cell strings; and

a plurality of CAM memory cell structures, wherein each CAM memory cell structure contains a paired first and second non-volatile memory cell from a first and second NAND memory cell strings, and where a control gate of the first and second memory cells of each CAM memory cell structure are coupled to a common word line;

wherein the first memory cell of each CAM memory cell structure is coupled through the source-side connection of the first NAND memory cell string to a non-inverting output of a selected bit position of the search word register and the second memory cell is coupled through the source-side connection of the second NAND memory cell string to an inverting output of a selected bit position of the search word register;

wherein the NAND architecture CAM memory device is adapted to precharge or pull-up the match line to a high logic signal; and

wherein a plurality of CAM memory cell structures of a selected word line of the plurality of NAND strings are read and if the selected word line stores a data word that does not match an input data word stored in the search word register the match line is pulled low and if the selected word line of the plurality of NAND strings storing a data word matching the input data word the match line left precharged or pulled high.

7. The NAND architecture CAM memory device of claim 6, wherein each word line of the plurality of NAND architecture memory cell strings is selected in turn to compare the data word stored in the plurality of CAM memory cell structures of each word line against the input data word.

8. The NAND architecture CAM memory device of claim 7, wherein a section of the non-volatile memory array is pre-selected to be scanned for matches to the input data word of the search word register.

9. The NAND architecture CAM memory device of claim 1, further comprising:

a search word register having an inverting and non-inverting output for each bit position of the search word register, wherein each output of the search word register is coupled to one or more word lines of the plurality of NAND memory cell strings;

a source line coupled to a source-side connection of the plurality of NAND memory cell strings; and

a plurality of match lines, each match line coupled to a drain-side connection of a NAND string of the plurality of NAND strings;

wherein each NAND memory cell string of the plurality of NAND memory cell strings stores a data word in a plurality of CAM memory cell structures, each CAM memory cell structure formed by a paired first and second non-volatile memory cells of the NAND memory cell string;

wherein a control gate of the first non-volatile memory cell of each CAM memory cell structure is coupled to a non-inverting output of a selected bit position of the search word register and a control gate of the second non-volatile memory cell is coupled to an inverting output of the selected bit position of the search word register; and

wherein a NAND string storing a data word matching an input data word stored in the search word register is adapted to couple a voltage of the source line to its coupled match line indicating a match.

10. The NAND architecture CAM memory device of claim 1, further comprising a decoder, wherein the decoder is adapted to pre-decode a section of the non-volatile memory array to search for the input data word by one of decoding all or some of the input data, where the pre-decoding is one of a binary address decoding, a hash algorithm decoding, a binary search tree decoding, and sequential hierarchal table decoding.

11. The NAND architecture CAM memory device of claim 1, further comprising:

an encoder/prioritizer circuit, wherein the encoder/prioritizer circuit is adapted to one or more of encode an address for a data match, indicate multiple matches, indicate a non-match, and select a priority match.

12. The NAND architecture CAM memory device of claim 1, wherein the NAND architecture CAM memory device is adapted to output additional associated data stored with a data word that matches the input data word.

13. A content addressable memory (CAM) device, comprising:

a non-volatile memory array having a plurality of non-volatile memory cells arranged in a plurality of NAND architecture memory cell strings;

an address decoder coupled to a plurality of word lines of the plurality of NAND memory cell strings;

a search word register having an inverting and non-inverting output for each bit position of the search word register, wherein each output of the search word register is coupled to a source-side connection of a NAND memory cell string of the plurality of NAND memory cell strings;

a match line coupled to a plurality of drain-side connections of the plurality of NAND memory cell strings; and

a plurality of CAM memory cell structures, wherein each CAM memory cell structure contains a paired first and second non-volatile memory cell from a first and second NAND memory cell strings, and where a control gate of the first and second non-volatile memory cells of each CAM memory cell structure are each coupled to a common word line;

wherein the first non-volatile memory cell of each CAM memory cell structure is coupled through the source-side connection of the first NAND memory cell string to a non-inverting output of a selected bit position of the search word register and the second non-volatile memory cell is coupled through the source-side connection of the second NAND memory cell string to an inverting output of a selected bit position of the search word register; and

wherein the CAM memory device is adapted to precharge or weakly pull the match line to a high or low logic signal.

14. The CAM memory device of claim 13, wherein the match line is precharged or weakly pulled to a logic high signal and where a selected word line of the plurality of NAND strings stores a data word that does not match an input data word stored in the search word register the match line is pulled low.

15. The CAM memory device of claim 13, wherein the match line is precharged or weakly pulled to a logic low signal and where if a selected word line of the plurality of NAND strings stores a data word that does not match an input data word stored in the search word register the match line is pulled high.

16. The CAM memory device of claim 13, wherein each word line of the plurality of NAND architecture memory cell strings is selected in turn to compare the data word stored in the plurality of CAM memory cell structures of each word line against the input data word.

17. The CAM memory device of claim 13, wherein a section of the non-volatile memory array to be scanned for matches is pre-selected based on the input data word.

18. The CAM memory device of claim 17, wherein the section of the non-volatile memory array to be scanned for matches is pre-selected based on the input data word by one of decoding all or some of the input data as a binary address, a hash algorithm decoding, a binary search tree, and sequential hierarchal table decoding with a hardware decoder circuit or a control circuit.

19. The CAM memory device of claim 13, further comprising:

an encoder/prioritizer circuit, wherein the encoder/prioritizer circuit is adapted to one or more of encode an address for a data match, indicate multiple matches, indicate a non-match, and select a priority match.

20. The CAM memory device of claim 13, wherein the CAM memory device is adapted to output additional associated data stored with data word that matches the input data word.

21. The CAM memory device of claim 13, wherein the CAM memory device is adapted to store ternary data in each CAM memory cell structure by:

leaving a first non-volatile memory cell coupled to a non-inverting search word register output for a CAM memory cell structure for a bit position erased and programming a second non-volatile memory cell coupled to an inverting search word register output for the bit position to store a “

1”

in the CAM memory cell structure;

programming the first non-volatile memory cell coupled to the non-inverting search word register output for the bit position and leaving erased the second non-volatile memory cell coupled to the inverting search word register output for the bit position to store a “

0”

in the CAM memory cell structure; and

programming both the first and second transistors to store a “

X”

or don'"'"'t care in the CAM memory cell.

22. The CAM memory device of claim 13, wherein the CAM memory device is adapted to store ternary data in each CAM memory cell structure by:

leaving a first non-volatile memory cell coupled to a non-inverting search word register output for a CAM memory cell structure for a bit position erased and programming a second non-volatile memory cell coupled to an inverting search word register output for the bit position to store a “

0”

in the CAM memory cell structure;

programming the first non-volatile memory cell coupled to the non-inverting search word register output for the bit position and leaving erased the second non-volatile memory cell coupled to the inverting search word register output for the bit position to store a “

1”

in the CAM memory cell structure; and

programming both the first and second transistors to store a “

X”

or don'"'"'t care in the CAM memory cell.

23. A content addressable memory (CAM) device, comprising:

a non-volatile memory array having a plurality of non-volatile memory cells arranged in a plurality of NAND architecture memory cell strings;

a search word register having an inverting and non-inverting output for each bit position of the search word register, wherein each output of the search word register is coupled to a plurality of word lines of the plurality of NAND memory cell strings;

a source line coupled to one or more source-side connections of the plurality of NAND memory cell strings; and

a plurality of match lines, each match line coupled to a drain-side connection of a NAND string of the plurality of NAND strings;

wherein each NAND memory cell string of the plurality of NAND memory cell strings stores a data word in a plurality of CAM memory cell structures and where each CAM memory cell structure is formed from a paired first and second non-volatile memory cells of the NAND memory cell string;

wherein a control gate of the first non-volatile memory cell of each CAM memory cell structure is coupled to a non-inverting output of a selected bit position of the search word register and a control gate of the second non-volatile memory cell is coupled to an inverting output of a selected bit position of the search word register; and

wherein the CAM memory device is adapted to couple a voltage of the source line through a NAND memory cell string to its coupled match line when a data word stored in the NAND memory cell string matches an input data word stored in the search word register.

24. The CAM memory device of claim 23, further comprising a sense amplifier/encoder coupled to the plurality of match lines to sense and encode a matching data word address from a match line indicating a matching data word is stored in a coupled NAND string.

25. The CAM memory device of claim 23, wherein a section of the non-volatile memory array to be scanned for matches is pre-selected based on the input data word.

26. The CAM memory device of claim 25, wherein the section of the non-volatile memory array to be scanned for matches is pre-selected based on the input data word is pre-selected by one of decoding all or some of the input data as a binary address, a hash algorithm decoding, a binary search tree, and sequential hierarchal table decoding with a hardware decoder circuit or a control circuit.

27. The CAM memory device of claim 23, further comprising:

an encoder/prioritizer circuit, wherein the encoder/prioritizer circuit is adapted to one or more of encode an address for a data match, indicate multiple matches, indicate a non-match, and select a priority match.

28. The CAM memory device of claim 23, wherein the CAM memory device is adapted to output additional associated data stored with data word that matches the input data word.

29. The CAM memory device of claim 23, wherein the CAM memory device is adapted to store ternary data in each CAM memory cell structure by:

programming a first non-volatile memory cell coupled to a non-inverting search word register output for a CAM memory cell structure for a bit position and leaving erased a second non-volatile memory cell coupled to an inverting search word register output for the bit position to store a “

1”

in the CAM memory cell structure;

leaving erased the first non-volatile memory cell coupled to the non-inverting search word register output for the bit position and programming the second non-volatile memory cell coupled to the inverting search word register output for the bit position to store a “

0”

in the CAM memory cell structure; and

leaving erased both the first and second transistors to store a “

X”

or don'"'"'t care in the CAM memory cell.

30. The CAM memory device of claim 23, wherein the CAM memory device is adapted to mask the data stored in a selected CAM memory cell structure of a NAND memory cell string by driving the control gates of the first and second transistors with a pass voltage.

31. The CAM memory device of claim 23, wherein the CAM memory device is adapted to disable or invalidate a NAND memory cell string by programming both the first and second non-volatile memory cells of one or more CAM memory cell structures of the NAND memory cell string.

32. The CAM memory device of claim 23, wherein the CAM memory device is adapted to precharge or weakly pull a match line to a high or low logic signal.

33. A content addressable memory (CAM) device, comprising:

a non-volatile Flash memory array having a plurality of non-volatile memory cells arranged in rows and columns in a plurality of NAND architecture memory cell strings; and

a control circuit;

wherein the CAM memory device is adapted to search the non-volatile Flash memory array for a data word input to a search register to locate a match.

34. The CAM memory device of claim 33, wherein the CAM memory device is adapted to search the non-volatile Flash memory array for a data word input to a search register to locate a match by scanning the Flash memory array to locate a matching data word and/or pre-selecting the section of the Flash memory array based on the input data word.

35. The CAM memory device of claim 34, wherein the CAM memory device is adapted to search the non-volatile Flash memory array for a data word input to a search register to locate a match by pre-selecting the section of the Flash memory array to scan based on the input data word by one of software pre-selection by the control circuit and hardware pre-decoding by decoder.

36. The CAM memory device of claim 34, wherein the CAM memory device is adapted to pre-select the section of the Flash memory array utilizing one of decoding all or some of the input data as a binary address, a hash algorithm decoding, a binary search tree, and sequential hierarchal table decoding.

37. The CAM memory device of claim 33, further comprising

a sense amplifier, wherein the sense amplifier has a comparator to compare one or more data words sensed from the non-volatile Flash memory array to a data word input to the search register.

38. A system, comprising:

a host coupled to a content addressable memory (CAM) device, where the CAM memory device comprises;

a non-volatile memory array having a plurality of non-volatile memory cells arranged in rows and columns in a plurality of NAND architecture memory cell strings; and

a control circuit;

wherein the CAM memory device is adapted to search the non-volatile memory array for a data word input to a search register to locate a match.

39. The system of claim 38, wherein the host is one of a processor and a memory controller.

40. The system of claim 38, wherein the non-volatile memory cells are one of non-volatile memory cells, multi-level cells (MLCs), and non-conductive floating node memory cells.

41. A method of operating a content addressable memory (CAM) device, comprising:

storing a plurality of data words in a plurality of NAND architecture memory cell strings of a NAND architecture Flash memory array; and

accessing the plurality of NAND architecture memory cell strings of a NAND architecture Flash memory array to locate a match for an input data word in the plurality of stored data words with a control circuit of the CAM memory device.

42. The method of claim 41, further comprising outputting one or more of a match address, a match location, a match/no-match indication signal, a multiple match indication signal, and associated information stored with a matching data word.

43. The method of claim 42, further comprising prioritizing a match address or location to output from the CAM memory device if two or more data words stored in the NAND architecture Flash memory array match the input data word.

44. The method of claim 41, further comprising pre-decoding the input data word to select a section of the non-volatile Flash memory array to search for the input data word, where the pre-decoding is one of decoding all or some of the input data as a binary address, a hash algorithm decoding, a binary search tree, and sequential hierarchal table decoding.

45. A method of operating a content addressable memory (CAM) device, comprising:

storing a plurality of data words in a plurality of NAND architecture memory cell strings of a NAND architecture non-volatile memory array, where each data word of the plurality of data words is stored in a row of the NAND architecture non-volatile memory array in a plurality of CAM memory cell structures, where each CAM memory cell structure having a first non-volatile memory cell and a second non-volatile memory cell from a first and second NAND architecture memory cell strings, respectively, of the row; and

comparing a selected stored data word of the plurality of stored data words with an input data word by,

precharging or weakly pulling a match line coupled to a drain-side connection of a plurality of NAND architecture memory cell strings of the NAND architecture non-volatile memory array to a high or low signal voltage level,

applying a read voltage to a word line coupled to a plurality of memory cells of the plurality of NAND architecture memory cell strings of a selected row of the NAND architecture non-volatile memory array,

applying a pass voltage to a plurality of unselected word lines, each unselected word line coupled to a plurality of unselected memory cells of the plurality of NAND architecture memory cell strings, and

applying the input data word to a plurality of source-side connections of the plurality of NAND architecture memory cell strings coupled to the selected row of the NAND architecture non-volatile memory array, such that the first non-volatile memory cell of each CAM memory cell structure is coupled through the source-side connection of the first NAND memory cell string of the CAM memory cell structure to an output of a selected bit position of the input data word and the second non-volatile memory cell is coupled through the source-side connection of the second NAND memory cell string of the CAM memory cell structure to an inverted output of the selected bit position of the input data word, and

sensing the match line.

46. The method of claim 45, wherein if the match line remains high the stored data word of the selected row matches the input data word.

47. The method of claim 45, further comprising scanning a plurality of rows of the NAND architecture non-volatile memory array to compare the input data word to a plurality of stored data words to locate a match.

48. The method of claim 45, further comprising pre-selecting a section of the non-volatile memory array to be scanned for matches based on the input data word by one of decoding all or some of the input data as a binary address, a hash algorithm decoding, a binary search tree, and sequential hierarchal table decoding.

49. The method of claim 45, wherein storing each data word of the plurality of data words in a row of the NAND architecture non-volatile memory array in a plurality of CAM memory cell structures further comprises,

for each CAM memory cell structure storing a bit position of the stored data word;

leaving the first non-volatile memory cell of the CAM memory cell structure for the bit position erased and programming the second non-volatile memory cell for the bit position to store a “

1”

in the CAM memory cell structure;

programming the first non-volatile memory cell for the bit position and leaving erased the second non-volatile memory cell for the bit position to store a “

0”

in the CAM memory cell structure; and

programming both the first and second transistors to store a “

X”

or don'"'"'t care for the bit position in the CAM memory cell structure.

50. The method of claim 45, wherein storing each data word of the plurality of data words in a row of the NAND architecture non-volatile memory array in a plurality of CAM memory cell structures further comprises,

for each CAM memory cell structure storing a bit position of the stored data word;

leaving the first non-volatile memory cell of the CAM memory cell structure for the bit position erased and programming the second non-volatile memory cell for the bit position to store a “

0”

in the CAM memory cell structure;

programming the first non-volatile memory cell for the bit position and leaving erased the second non-volatile memory cell for the bit position to store a “

1”

in the CAM memory cell structure; and

programming both the first and second transistors to store a “

X”

or don'"'"'t care for the bit position in the CAM memory cell structure.

51. A method of operating a content addressable memory (CAM) device, comprising:

storing a plurality of data words in a plurality of NAND architecture memory cell strings of a NAND architecture non-volatile memory array, where each data word of the plurality of data words is stored in a selected NAND architecture memory cell string of the NAND architecture non-volatile memory array in a plurality of CAM memory cell structures, each CAM memory cell structure having a first non-volatile memory cell and a second non-volatile memory cell coupled in the selected NAND architecture memory cell string; and

comparing the plurality of stored data words to an input data word by, applying a voltage to a source line coupled to a source-side connection of the plurality of NAND memory cell strings of the NAND architecture non-volatile memory array,

applying the input data word to a plurality word lines, each word line coupled to a plurality of memory cells of the plurality of NAND architecture memory cell strings, wherein a control gate of the first non-volatile memory cell of each CAM memory cell structure is coupled to a word line driven by an output of a selected bit position of the input data word and where a control gate of the second non-volatile memory cell is coupled to a word line coupled to an inverted output of the selected bit position of the input data word, and

sensing a plurality of match lines coupled to a drain-side connection of the plurality of NAND architecture memory cell strings.

52. The method of claim 51, further comprising scanning a plurality of sections of the NAND architecture non-volatile memory array to locate a match to the input data word.

53. The method of claim 51, further comprising pre-selecting a section of the non-volatile memory array to be scanned for matches based on the input data word by one of decoding all or some of the input data as a binary address, a hash algorithm decoding, a binary search tree, and sequential hierarchal table decoding.

54. The method of claim 51, wherein storing each data word of the plurality of data words in a NAND architecture memory string of the NAND architecture non-volatile memory array in a plurality of CAM memory cell structures further comprises,

for each CAM memory cell structure storing a bit position of the stored data word;

leaving a first non-volatile memory cell for the bit position erased and programming a second non-volatile memory cell for the bit position to store a “

0”

in the CAM memory cell structure;

programming the first non-volatile memory cell for the bit position and leaving erased the second non-volatile memory cell for the bit position to store a “

1”

in the CAM memory cell structure; and

leaving both the first and second transistors erased to store a “

X”

or don'"'"'t care for the bit position in the CAM memory cell structure.