CIRCUITS, METHODS AND DESIGN STRUCTURES FOR ADAPTIVE REPAIR OF SRAM ARRAYS
First Claim
1. A static random access memory circuit comprising:
- a static random access memory array having a plurality of cells, in turn having a plurality of devices;
a global sensor having at least one output, coupled to said static random access memory array, and configured to sense at least one of global readability and global write-ability;
a decision-making circuit coupled to said at least one output of said global sensor, said decision-making circuit being configured to determine, from said at least one output of said global sensor, whether adaptation signals are required to correct said at least one of global readability and write-ability; and
an adaptation signal generation block, coupled to said decision-making circuit and said array, and configured to supply said adaptation signals to said array, responsive to said decision-making circuit determining that said adaptation signals are required;
wherein at least said array and said global sensor are realized in a single integrated circuit.
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Accused Products
Abstract
The circuit includes a static random access memory array having a plurality of cells, in turn having a plurality of devices; as well as a global sensor having at least one output, coupled to the static random access memory array, and configured to sense at least one of global readability and global write-ability. Also included is a decision-making circuit coupled to the at least one output of the global sensor. The decision-making circuit is configured to determine, from the at least one output of the global sensor, whether adaptation signals are required to correct global readability and/or write-ability. An adaptation signal generation block is also included and is coupled to the decision-making circuit and the array, and configured to supply the adaptation signals to the array, responsive to the decision-making circuit determining that the adaptation signals are required. At least the array and the global sensor, and preferably the decision-making circuit and the adaptation signal generation block as well, are implemented on a single integrated circuit chip. An associated method and design structure(s) are also provided.
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Citations
20 Claims
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1. A static random access memory circuit comprising:
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a static random access memory array having a plurality of cells, in turn having a plurality of devices; a global sensor having at least one output, coupled to said static random access memory array, and configured to sense at least one of global readability and global write-ability; a decision-making circuit coupled to said at least one output of said global sensor, said decision-making circuit being configured to determine, from said at least one output of said global sensor, whether adaptation signals are required to correct said at least one of global readability and write-ability; and an adaptation signal generation block, coupled to said decision-making circuit and said array, and configured to supply said adaptation signals to said array, responsive to said decision-making circuit determining that said adaptation signals are required; wherein at least said array and said global sensor are realized in a single integrated circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method for compensating static random access memory chips, said method comprising the steps of:
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obtaining a plurality of said chips, each of said chips comprising; a static random access memory array having a plurality of cells, in turn having a plurality of devices; a global sensor having at least one output, coupled to said static random access memory array, and configured to sense at least one of global readability and global write-ability; a decision-making circuit coupled to said at least one output of said global sensor, said decision-making circuit being configured to determine, from said at least one output of said global sensor, whether adaptation signals are required to correct said at least one of global readability and write-ability; and an adaptation signal generation block, coupled to said decision-making circuit and said array, and configured to supply said adaptation signals to said array, responsive to said decision-making circuit determining that said adaptation signals are required; testing each of said chips to determined whether at least one of read and write compensation is required; for those of said chips for which neither read nor write compensation is required, designating said chips as “
good”
;performing write compensation for those of said chips where write compensation is required; performing read compensation for those of said chips where read compensation is required; and re-testing those of said chips where at least one of read and write compensation was performed, wherein those of said chips which pass said re-test are designated as “
good” and
those of said chips which fail said re-test are designated as “
faulty.”
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15. A design structure embodied in a machine readable medium, said design stricture comprising a static random access memory circuit, said static random access memory circuit in turn comprising:
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a static random access memory array having a plurality of cells, in turn having a plurality of devices; a global sensor having at least one output, coupled to said static random access memory array, and configured to sense at least one of global readability and global write-ability; a decision-making circuit coupled to said at least one output of said global sensor, said decision-making circuit being configured to determine, from said at least one output of said global sensor, whether adaptation signals are required to correct said at least one of global readability and write-ability; and an adaptation signal generation block, coupled to said decision-making circuit and said array, and configured to supply said adaptation signals to said array, responsive to said decision-making circuit determining that said adaptation signals are required; wherein at least said array and said global sensor are realized in a single integrated circuit. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification