System to Enable a Memory Hub Device to Manage Thermal Conditions at a Memory Device Level Transparent to a Memory Controller

• US 20090190427A1
• Filed: 01/24/2008
• Published: 07/30/2009
• Est. Priority Date: 01/24/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gower, Kevin C., Maule, Warren E., Brittain, Mark A.
• Granted Patent: US 7,930,470 B2
• Time in Patent Office: Days
• US Class Current: 365/212
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory system is provided that manages thermal conditions at a memory device level transparent to a memory controller. The memory systems comprises a memory hub device integrated in a memory module, a set of memory devices coupled to the memory hub device, and a first set of thermal sensors integrated in the set of memory devices. A thermal management control unit integrated in the memory hub device monitors a temperature of the set of memory devices sensed by the first set of thermal sensors. The memory hub device reduces a memory access rate to the set of memory devices in response to a predetermined thermal threshold being exceeded thereby reducing power used by the set of memory devices which in turn decreases the temperature of the set of memory devices.

Claims

1. A memory system, comprising:

a memory hub device integrated in a memory module;

a set of memory devices coupled to the memory hub device; and

a first set of thermal sensors integrated in the set of memory devices.

2. The memory system of claim 1, wherein a thermal management control unit integrated in the memory hub device monitors a temperature of the set of memory devices sensed by the first set of thermal sensors and wherein the memory hub device reduces a memory access rate to the set of memory devices in response to a predetermined thermal threshold being exceeded thereby reducing power used by the set of memory devices which in turn decreases the temperature of the set of memory devices.

3. The memory system of claim 1, further comprising:

a second set of thermal sensors integrated in the memory hub device, wherein the memory hub device monitors the temperature of the memory hub device sensed by the second set of thermal sensors and wherein the memory hub device reduces a memory access rate to the set of memory devices in response to the predetermined thermal threshold being exceeded thereby reducing power used by the set of memory devices which in turn decreases the temperature of the memory hub device.

4. The memory system of claim 1, wherein the memory hub device comprises:

a command queue that receives a memory access command from an external memory controller via a memory channel at a first operating frequency;

a write data queue that receives memory write data from the external memory controller via the memory channel at the first operating frequency; and

a read data queue that transmits memory read data from the external memory controller via the memory channel at the first operating frequency; and

a memory hub controller integrated in the memory hub device, wherein the memory hub controller;

reads the memory access command from the command queue at a second operating frequency;

reads the memory write data from the write data queue at the second operating frequency; and

writes the read data to the read data queue at the second operating frequency, wherein receiving the memory access command, receiving the write data, and transmitting the read data at the first operating frequency and reading the memory access command, reading the write data, and writing the read data at the second operating frequency implements a fully asynchronous boundary within the memory hub device.

5. The memory system of claim 1, wherein the memory hub device further comprises:

a memory device data interface, coupled to a read data queue, a write data queue, and the set of memory devices, that provides a communication path between the set of memory devices and the read data queue or the write data queue.

6. The memory system of claim 5, wherein the memory hub controller controls the transfer of data between the write data queue and the set of memory devices and the transfer of data between the set of memory devices and the read data queue.

7. The memory system of claim 1, wherein the memory hub device further comprises:

a link interface, coupled to a memory device data interface, that provides a communication path between the memory module and the external memory controller, and wherein the memory hub controller controls the transfer of data between the memory device data interface and the link interface.

8. The memory system of claim 1, wherein the memory hub device further comprises:

a link interface, coupled to the memory hub controller, that provides a communication path between the memory module and the external memory controller, and wherein the memory hub controller controls the transfer of the memory access command from the link interface to the set of memory devices.

9. The memory system of claim 8, wherein the memory hub controller further comprises:

a memory device sequencer that determines a proper clock cycle to issue the memory access command to the set of memory devices.

10. The memory system of claim 9, wherein the proper clock cycle is determined based on at least one of the specification of the set of memory devices or previous memory access commands sent to the set of memory devices.

11. The memory system of claim 1, wherein the memory module is one of a dual in-line memory module (DIMM) or a single in-line memory module (SIMM).

12. The memory system of claim 1, wherein the memory module is part of a data processing device.

13. A data processing system, comprising:

a processor; and

a memory coupled to the processor, wherein the memory comprises one or more memory modules, each memory module comprising;

a memory hub device integrated in the memory module;

a set of memory devices coupled to the memory hub device; and

a first set of thermal sensors integrated in the set of memory devices.

14. The data processing system of claim 13, wherein a thermal management control unit integrated in the memory hub device monitors a temperature of the set of memory devices sensed by the first set of thermal sensors and wherein the memory hub device reduces a memory access rate to the set of memory devices in response to a predetermined thermal threshold being exceeded thereby reducing power used by the set of memory devices which in turn decreases the temperature of the set of memory devices.

15. The data processing system of claim 13, further comprising:

a second set of thermal sensors integrated in the memory hub device, wherein the memory hub device monitors the temperature of the memory hub device sensed by the second set of thermal sensors and wherein the memory hub device reduces a memory access rate to the set of memory devices in response to the predetermined thermal threshold being exceeded thereby reducing power used by the set of memory devices which in turn decreases the temperature of the memory hub device.

16. The data processing system of claim 13, wherein the memory hub device comprises:

a command queue that receives a memory access command from an external memory controller via a memory channel at a first operating frequency;

a write data queue that receives memory write data from the external memory controller via the memory channel at the first operating frequency; and

a read data queue that transmits memory read data from the external memory controller via the memory channel at the first operating frequency; and

a memory hub controller integrated in the memory hub device, wherein the memory hub controller;

reads the memory access command from the command queue at a second operating frequency;

reads the memory write data from the write data queue at the second operating frequency; and

writes the read data to the read data queue at the second operating frequency, wherein receiving the memory access command, receiving the write data, and transmitting the read data at the first operating frequency and reading the memory access command, reading the write data, and writing the read data at the second operating frequency implements a fully asynchronous boundary within the memory hub device.

17. The data processing system of claim 13, wherein the memory hub device further comprises:

a memory device data interface, coupled to a read data queue, a write data queue, and the set of memory devices, that provides a communication path between the set of memory devices and the read data queue or the write data queue.

18. The data processing system of claim 13, wherein the memory hub device further comprises:

a link interface, coupled to a memory device data interface, that provides a communication path between the memory module and the external memory controller, and wherein the memory hub controller controls the transfer of data between the memory device data interface and the link interface.

19. The data processing system of claim 13, wherein the memory hub device further comprises:

a link interface, coupled to the memory hub controller, that provides a communication path between the memory module and the external memory controller, and wherein the memory hub controller controls the transfer of the memory access command from the link interface to the set of memory devices.

20. A method for managing thermal conditions at a memory device level transparent to a memory controller, comprising:

monitoring, by a thermal management control unit integrated in a memory hub device of a memory module, a temperature of a set of memory devices sensed by a set of thermal sensors integrated in the set of memory devices, wherein the set of memory devices are coupled to the memory hub device; and

reducing, by the memory hub device, a memory access rate to the set of memory devices in response to a predetermined thermal threshold being exceeded thereby reducing power used by the set of memory devices which in turn decreases the temperature of the set of memory devices.