SYSTEMS AND METHODS FOR TEST TIME OUTLIER DETECTION AND CORRECTION IN INTEGRATED CIRCUIT TESTING

• US 20090192754A1
• Filed: 04/03/2009
• Published: 07/30/2009
• Est. Priority Date: 07/06/2005
• Status: Active Grant

• Current Assignee: Optimal Plus Ltd. (Emerson Electric Company)
• Original Assignee: Optimaltest, Ltd. (Emerson Electric Company)
• Inventors: Linde, Reed, Balog, Gil, Golan, Avi
• Granted Patent: US 7,969,174 B2
• Time in Patent Office: Days
• US Class Current: 702/117
• CPC Class Codes: G01R 31/2601 Apparatus or methods therefor G01R31/2607, G01R31/2642 take precedence
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/3172 Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing
• CPC Class Codes: G01R 31/318511 Wafer Test

Abstract

Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.

Claims

1. A system for semiconductor testing, comprising:

an algorithm engine, external to a tester, configured to recognize that a device is testing too slowly and that a test program should be aborted;

said algorithm engine configured to indicate to a tester to abort said test program on said semiconductor device.

2. The system of claim 1, further comprising:

a tester configured apply a said test program on said semiconductor device.

3. The system of claim 2, wherein said tester is further configured to generate monitor data, and wherein said algorithm engine is configured to recognize that said device is testing too slowly and that said test program should be aborted based on at least part of said generated monitor data.

4. The system of claim 3, wherein said tester includes at least one monitor data generator selected from a group comprising:

test time monitor, test status monitor, and yield monitor.

5. The system of claim 2, wherein said tester is further configured to apply said test program to said device in parallel with at least one other device.

6. The system of claim 2, wherein said test program includes test time limits for individual tests in said test program, and wherein said algorithm engine is configured to recognize that a device is testing too slowly even though said test limits in said test program have not been exceeded.

7. The system of claim 1, wherein said algorithm engine is configured to recognize that said device is testing too slowly and said test program should be aborted based on at least one parameter setting.

8. The system of claim 7, further comprising:

at least one selected from test program settings module, and rules and threshold settings module configured to provide said at least one parameter setting.

9. The system of claim 7, wherein said at least one parameter setting comprises at least one selected from a group comprising:

maximum test time value for a test, maximum test time value for a test program, typical test time value for a test, typical test time value for a test program, maximum number of too-slow testing devices allowed to have testing aborted, maximum test time for a plurality of tests, typical test time for a plurality of tests, and an entry in a look up table indicating whether a device undergoing a test is testing too slowly.

10. The system of claim 7, wherein a setting for one of said parameters depends on which group of semiconductor devices with an assumed common response to testing includes said semiconductor device.

11. The system of claim 7, wherein a setting for one of said parameters varies over time.

12. The system of claim 7, wherein a setting for one of said parameters depends on at least one test factory condition.

13. The system of claim 1, wherein said algorithm engine is further configured based on a received indication to proceed with evaluating or suspend evaluating whether said device is testing too slowly and said test program should be aborted.

14. The system of claim 13, further comprising:

at least one watchdog timer configured to provide said indication received by said algorithm engine.

15. The system of claim 1, wherein said algorithm engine is configured to recognize that said device is testing too slowly in comparison to at least one other device being tested in parallel.