SYSTEM AND METHOD FOR PROVIDING COPYBACK DATA INTEGRITY IN A NON-VOLATILE MEMORY SYSTEM

• US 20090193058A1
• Filed: 01/29/2008
• Published: 07/30/2009
• Est. Priority Date: 01/29/2008
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Denali Software Incorporated (Cadence Group)
• Inventors: Reid, Robert Alan
• Granted Patent: US 8,271,515 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

An invention is provided for affording CopyBack data integrity in a non-volatile memory system. When the potential for moving data with a CopyBack command occurs, a counter corresponding to the data is examined. When the counter is below a predetermined limit, the counter is incremented and data from the block of data is moved using a CopyBack command. However, when the counter reaches the predetermined limit, the counter is reset and data from the block of data is moved to system memory and examined for errors. Once any errors are corrected, the data is transferred back to the non-volatile memory.

Claims

1. A method for providing CopyBack data integrity in a non-volatile memory system, comprising the operations of:

examining a counter corresponding to data in a block of data;

adjusting the counter and moving data from the block of data using a CopyBack command when the counter has not reached a predetermined limit; and

resetting the counter and examining data from the block of data for errors when the counter reaches the predetermined limit.

2. A method as recited in claim 1, wherein the block of data comprises a plurality of pages of data.

3. A method as recited in claim 2, wherein data from at least one page of the plurality of pages is transferred to a corresponding page in a new block using a CopyBack command when the counter has not reached the predetermined limit.

4. A method as recited in claim 2, wherein data from at least one page of the plurality of pages is transferred to system memory and examined for errors when the counter reaches the predetermined limit.

5. A method as recited in claim 4, wherein an error in the data from the at least one page of data is corrected while the data is stored in system memory.

6. A method as recited in claim 5, wherein the data from the at least one page of data is transferred to a corresponding page in a new block of the non-volatile memory system after the error is corrected.

7. A method as recited in claim 1, wherein the predetermined limit is based on a probability of accumulated defects exceeding an error correction capability of the non-volatile memory system.

8. A non-volatile memory system capable of providing CopyBack data integrity, comprising:

a non-volatile memory having a plurality of blocks, each block comprising a plurality of pages, the non-volatile memory being capable of moving a page of data from one block to another using a CopyBack operation; and

a non-volatile memory controller coupled to the non-volatile memory, the non-volatile memory controller capable of examining a counter corresponding to a data stored in a block, the non-volatile memory controller having logic that adjusts the counter and issues a CopyBack command to move data from the block to another block when the counter has not reached a predetermined limit, the non-volatile memory controller further having logic that resets the counter and transfers data from the block to system memory when the counter reaches the predetermined limit.

9. A non-volatile memory system as recited in claim 8, wherein the non-volatile memory controller issues a CopyBack command to transfer data from at least one page to a corresponding page in a new block when the counter has not reached the predetermined limit.

10. A non-volatile memory system as recited in claim 8, wherein the non-volatile memory controller transfers data from at least one page to system memory when the counter reaches the predetermined limit.

11. A non-volatile memory system as recited in claim 10, wherein an error in the data from the at least one page is corrected while the data is stored in system memory.

12. A non-volatile memory system as recited in claim 11, wherein the non-volatile memory controller transfers the data from the at least one page to a corresponding page in a new block of the non-volatile memory device after the error is corrected.

13. A non-volatile memory system as recited in claim 8, wherein the predetermined limit is based on a probability of accumulated defects exceeding an error correction capability of the non-volatile memory system.

14. A non-volatile memory controller capable of providing CopyBack data integrity in a non-volatile memory system, comprising:

logic that examines a counter corresponding to data stored in a first block of data in a non-volatile memory;

logic that adjusts the counter and issues a CopyBack command to move data from the first block to a second block in the non-volatile memory when the counter has not reached a predetermined limit; and

logic that resets the counter and transfers data from the first block to system memory when the counter reaches the predetermined limit.

15. A non-volatile memory controller as recited in claim 14, wherein the non-volatile memory controller issues a CopyBack command to transfer data from a page in the first block to a corresponding page in the second block when the counter has not reached the predetermined limit.

16. A non-volatile memory controller as recited in claim 14, wherein the non-volatile memory controller transfers data from a page in the first block to system memory when the counter reaches the predetermined limit.

17. A non-volatile memory controller as recited in claim 16, wherein an error in the data from the page is corrected while the data is stored in system memory.

18. A non-volatile memory controller as recited in claim 17, wherein the non-volatile memory controller transfers the data from the page to a corresponding page in the second block after the error is corrected.

19. A non-volatile memory controller as recited in claim 14, wherein the predetermined limit is based on a probability of accumulated defects exceeding an error correction capability of the non-volatile memory system.

20. A non-volatile memory controller as recited in claim 19, wherein a separate counter is maintained for data stored in each page of memory.