Hybrid 2-Level Mapping Tables for Hybrid Block- and Page-Mode Flash-Memory System

• US 20090193184A1
• Filed: 04/03/2009
• Published: 07/30/2009
• Est. Priority Date: 12/02/2003
• Status: Abandoned Application

• Current Assignee: Super Talent Electronics, Inc.
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Shin, Myeongjin, Ma, Abraham C., Lee, Charles C., Yu, Frank
• Application Number:
  US12/418,550
• Publication Number:
  US 20090193184A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/00 Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A hybrid solid-state disk (SSD) has multi-level-cell (MLC) or single-level-cell (SLC) flash memory, or both. SLC flash may be emulated by MLC that uses fewer cell states. A NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Most data is block-mapped and stored in MLC flash, but some critical or high-frequency data is page-mapped to reduce block-relocation copying. A hybrid mapping table has a first-level and a second level. Only the first level is used for block-mapped data, but both levels are used for page-mapped data. The first level contains a block-page bit that indicates if the data is block-mapped or page-mapped. A PBA field in the first-level table maps block-mapped data, while a virtual field points to the second-level table where the PBA and page number is stored for page-mapped data. Page-mapped data is identified by a frequency counter or sector count. SRAM space is reduced.

Claims

1. A multi-level-controlled flash device comprising:

a smart storage switch which comprises;

an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address;

a smart storage transaction manager that manages transactions from the host;

a virtual storage processor that maps the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor performing a high level of mapping;

a virtual storage bridge between the smart storage transaction manager and a LBA bus;

a NVM controller, coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the host data from the virtual storage bridge; and

a hybrid mapper, in the NVM controller, that maps the LBA to a physical block address (PBA), the hybrid mapper generating the PBA for block-mapped host data, and the hybrid mapper generating the PBA and a page number for host data that is page-mapped;

a plurality of flash channels that include the assigned flash channel, wherein a flash channel comprises;

NVM flash memory, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the hybrid mapper in the NVM controller, and at a page location identified by the page number for the page-mapped host data;

whereby the hybrid mapper performs address mapping for block-mapped host data, and also performs address mapping for page-mapped host data to access the NVM flash memory.

2. The multi-level-controlled flash device of claim 1 wherein the hybrid mapper further comprises:

a first-level mapping table accessed by the hybrid mapper, the first-level mapping table having entries that store the PBA for block-mapped host data, and that store a virtual pointer when the host data is page-mapped; and

a second-level mapping table, accessed by the hybrid mapper and located by the virtual pointer read from entries in the first-level mapping table, the second-level mapping table having entries that store the PBA and a page number for host data that is page-mapped.

3. The multi-level-controlled flash device of claim 1 wherein the LBA bus comprises a Serial AT-Attachment (SATA) bus, a Serial small-computer system interface (SCSI) (SAS) bus, a fiber-channel (FC) bus, an InfiniBand bus, an integrated device electronics (IDE) bus, a Peripheral Components Interconnect Express (PCIe) bus, a compact flash (CF) bus, a Universal-Serial-Bus (USB), a Secure Digital Bus (SD), a MultiMediaCard (MMC), or a LBA bus protocol which transfers read and write commands, a starting page address with a sector offset, and a sector count.

4. The multi-level-controlled flash device of claim 2 wherein entries in the first-level mapping table further comprise:

a block-page bit that indicates when host data mapped by an entry is block-mapped and uses the PBA stored in the first-level mapping table, and when the host data is page-mapped and uses the virtual pointer to locate the second-level mapping table, and uses the PBA and the page number from an entry in the second-level mapping table,

whereby both block-mapped and page-mapped host data are identified by the block-page bit.

5. The multi-level-controlled flash device of claim 1 wherein the NVM flash memory comprise:

multi-level-cell (MLC) flash memory that stores multiple bits of data per physical flash-memory cell, wherein a physical flash-memory cell has at least four states generating at least four voltages during sensing for read;

single-level-cell (SLC) flash memory emulated by a portion of the MLC flash memory storing only one bit of data per physical flash-memory cell, wherein a physical flash-memory cell has two states;

wherein the MLC flash memory have a higher density than the SLC flash memory, and the SLC flash memory have a higher reliability than the MLC flash memory,

whereby flash memory is a hybrid flash memory with both MLC and SLC flash memory.

6. The multi-level-controlled flash device of claim 1 wherein the NVM flash memory comprises:

a portion for storing the block-mapped host data; and

another portion for storing the page-mapped host data;

wherein frequently-changed host data or host data with a sector count that is less than a sector count threshold are page-mapped;

wherein the NVM flash memory can be either MLC or SLC flash memories.

7. The multi-level-controlled flash device of claim 6 wherein the hybrid mapper further comprises:

a sector-count comparator that compares a sector count (SC) that identifies a number of sectors of the host data to a SC threshold and sets the block-page bit in the entry in the first-level mapping table to indicate block-mapped host data when the sector count exceeds the SC threshold, and clears block-page bit in the entry in the first-level mapping table to indicate page-mapped host data when the sector count does not exceed the SC threshold,

whereby the sector count determines when the host data is block-mapped and when the host data is page-mapped.

8. The multi-level-controlled flash device of claim 7 wherein entries in the first-level mapping table further comprise:

a frequency counter (FC) that indicates a relative number of times that host data mapped by an entry has been written;

wherein the hybrid mapper further comprises;

a frequency-count comparator that compares the frequency counter to a FC threshold and clears block-page bit in the entry in the first-level mapping table to indicate page-mapped host data when the frequency counter exceeds the FC threshold,

whereby the frequency counter determines when the host data is block-mapped and when the host data is page-mapped.

9. A hybrid-mapped solid-state disk comprising:

volatile memory buffer means for temporarily storing host data in a volatile memory that loses data when power is disconnected;

smart storage switch means for switching host commands to a plurality of downstream devices, the smart storage switch means comprising;

upstream interface means, coupled to a host, for receiving host commands to access flash memory and for receiving host data and a host address;

smart storage transaction manager means for managing transactions from the host;

virtual storage processor means for translating the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor means performing a first level of mapping;

virtual storage bridge means for transferring host data and the LBA between the smart storage transaction manager means and a LBA bus;

data striping means for dividing the host data into data segments that are assigned to different ones of the plurality of flash channels;

a plurality of flash channels that include the assigned flash channel, wherein a flash channel comprises;

lower-level controller means for controlling flash operations, coupled to the LBA bus to receive the LBA generated by the virtual storage processor means and the host data from the virtual storage bridge means;

hybrid mapper means, coupled to the lower-level controller means, for mapping the LBA to a physical block address (PBA);

first-level mapping table means, accessed by the hybrid mapper means, for storing entries that store the PBA for block-mapped host data, and that store a virtual pointer when the host data is page-mapped;

second-level mapping table means, accessed by the hybrid mapper means, and located by the virtual pointer read from entries in the first-level mapping table means, for storing second entries that store the PBA and a page number for host data that is page-mapped;

NVM flash memory means, coupled to the lower-level controller means, for storing the block-mapped host data at a block location identified by the PBA stored by the first-level mapping table means, and for storing the page-mapped host data at a page location identified by the PBA and the page number stored by the second-level mapping table means;

wherein the NVM flash memory means in the plurality of flash channels are non-volatile memory that retain data when power is disconnected,

whereby address mapping is performed at two levels for page-mode host data and at one level for block-mode host data to access the NVM flash memory means.

10. The hybrid-mapped solid-state disk of claim 9 wherein a stripe depth is equal to N times a stripe size, wherein N is a whole number of the plurality of flash channels, and wherein the stripe size is equal to a number of pages that can be simultaneously written into one of the plurality of flash channels.

11. The hybrid-mapped solid-state disk of claim 9 wherein the flash channel comprises a Non-Volatile-Memory Device (NVMD) that is physically mounted to a host motherboard through a connector and socket, by direct solder attachment, or embedded within the host motherboard.

12. The hybrid-mapped solid-state disk of claim 9 wherein the NVM flash memory means comprises a flash memory, a phase-change memory (PCM), ferroelectric random-access memory (FRAM), Magnetoresistive RAM (MRAM), Memristor, PRAM, SONOS, Resistive RAM (RRAM), Racetrack memory, or nano RAM (NRAM).

13. The hybrid-mapped solid-state disk of claim 9 wherein entries in the first-level mapping table means further comprise:

block-page means for indicating when host data mapped by an entry is block-mapped and uses the PBA stored in the first-level mapping table means, and when the host data is page-mapped and uses the virtual pointer to locate the second-level mapping table means, and uses the PBA and the page number from an entry in the second-level mapping table means,

whereby both block-mapped and page-mapped host data are identified by the block-page means.

14. The hybrid-mapped solid-state disk of claim 13 wherein the NVM flash memory means further comprise:

multi-level-cell (MLC) flash memory means for storing multiple bits of data per physical flash-memory cell, wherein a physical flash-memory cell has at least four states generating at least four voltages during sensing for read;

single-level-cell (SLC) flash memory means for storing only one bit of data per physical flash-memory cell, wherein a physical flash-memory cell has two states;

wherein the MLC flash memory means have a higher density than the SLC flash memory means, and the SLC flash memory means have a higher reliability than the MLC flash memory means,

whereby flash memory is a hybrid flash memory with both MLC and SLC flash memory means.

15. The hybrid-mapped solid-state disk of claim 13 wherein the NVM flash memory means further comprises:

block-mapped memory means for storing the block-mapped host data at a block location identified by the PBA stored by the first-level mapping table means;

page-mapped memory means for storing the page-mapped host data at a page location identified by the PBA and the page number stored by the second-level mapping table means;

wherein the block-mapped memory means occupies a larger portion of a total memory capacity than does the page-mapped memory means.

16. The hybrid-mapped solid-state disk of claim 15 wherein the hybrid mapper means further comprises:

sector-count comparator means for comparing a sector count (SC) that identifies a number of sectors of the host data to a SC threshold and sets the block-page means in the entry in the first-level mapping table means to indicate block-mapped host data when the sector count exceeds the SC threshold, and clears block-page means in the entry in the first-level mapping table means to indicate page-mapped host data when the sector count does not exceed the SC threshold,

whereby the sector count determines when the host data is block-mapped and when the host data is page-mapped.

17. A multi-level-controller device comprising:

a smart storage switch which comprises;

an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address;

a smart storage transaction manager that manages transactions from the host;

a virtual storage processor that maps the host address to an assigned flash module to generate a logical block address (LBA), the virtual storage processor performing a mapping for data striping;

a virtual storage bridge between the smart storage transaction manager and a LBA bus;

a volatile memory buffer for temporarily storing the host data in a volatile memory that loses data when power is disconnected;

wherein the volatile memory buffer operates as a write-through cache, a write-back cache, or a read-ahead cache;

a NVM controller, coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the host data from the virtual storage bridge;

a logical to physical address mapper, in the NVM controller, that maps the LBA to a physical block address (PBA);

a plurality of NVM devices (NVMD) that include the assigned NVMD, wherein a NVMD comprises;

raw-NAND flash memory chips, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the logical to physical mapper in the NVM controller;

whereby address mapping is performed to access the raw-NAND flash memory chips.

18. A logical-block-address (LBA) flash module comprising:

a substrate having wiring traces printed thereon, the wiring traces for conducting signals;

a plurality of metal contact pads along a first edge of the substrate, the plurality of contact pads for mating with a memory module socket on a board;

a plurality of Non-Volatile-Memory Devices (NVMD) mounted on the substrate for storing host data;

wherein the plurality of NVMD retain data when power is disconnected to the flash module;

a logical-block-address LBA bus formed by wiring traces on the substrate that connect to the plurality of metal contact pads;

wherein the plurality of NVMD are coupled by the LBA bus;

wherein the plurality of NVMD store host data sent over the plurality of metal pads at a block location identified by the LBA from the Host;

wherein the flash module connects the plurality of NVMD to the board through the LBA bus.

19. A logical-block-address (LBA) flash module comprising:

a substrate having wiring traces printed thereon, the wiring traces for conducting signals;

a plurality of metal contact pads along a first edge of the substrate, the plurality of contact pads for mating with a memory module socket on a board;

a plurality of Non-Volatile-Memory Devices (NVMD) mounted on the substrate for storing host data from a host;

wherein the plurality of NVMD retain data when power is disconnected to the flash module;

a logical-block-address LBA bus formed by wiring traces on the substrate that connect to the plurality of metal contact pads;

a Smart Switch Storage (SSS) Controller, mounted on the substrate, coupled to the LBA bus to receive a LBA from the board through the plurality of metal contact pads;

wherein the plurality of NVMD are coupled by the LBA bus to the SSS controller;

wherein the plurality of NVMD store host data sent over the plurality of metal pads at a block location identified by the LBA generated by the SSS controller.