Hybrid 2-Level Mapping Tables for Hybrid Block- and Page-Mode Flash-Memory System
First Claim
1. A multi-level-controlled flash device comprising:
- a smart storage switch which comprises;
an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address;
a smart storage transaction manager that manages transactions from the host;
a virtual storage processor that maps the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor performing a high level of mapping;
a virtual storage bridge between the smart storage transaction manager and a LBA bus;
a NVM controller, coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the host data from the virtual storage bridge; and
a hybrid mapper, in the NVM controller, that maps the LBA to a physical block address (PBA), the hybrid mapper generating the PBA for block-mapped host data, and the hybrid mapper generating the PBA and a page number for host data that is page-mapped;
a plurality of flash channels that include the assigned flash channel, wherein a flash channel comprises;
NVM flash memory, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the hybrid mapper in the NVM controller, and at a page location identified by the page number for the page-mapped host data;
whereby the hybrid mapper performs address mapping for block-mapped host data, and also performs address mapping for page-mapped host data to access the NVM flash memory.
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Accused Products
Abstract
A hybrid solid-state disk (SSD) has multi-level-cell (MLC) or single-level-cell (SLC) flash memory, or both. SLC flash may be emulated by MLC that uses fewer cell states. A NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Most data is block-mapped and stored in MLC flash, but some critical or high-frequency data is page-mapped to reduce block-relocation copying. A hybrid mapping table has a first-level and a second level. Only the first level is used for block-mapped data, but both levels are used for page-mapped data. The first level contains a block-page bit that indicates if the data is block-mapped or page-mapped. A PBA field in the first-level table maps block-mapped data, while a virtual field points to the second-level table where the PBA and page number is stored for page-mapped data. Page-mapped data is identified by a frequency counter or sector count. SRAM space is reduced.
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Citations
19 Claims
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1. A multi-level-controlled flash device comprising:
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a smart storage switch which comprises; an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address; a smart storage transaction manager that manages transactions from the host; a virtual storage processor that maps the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor performing a high level of mapping; a virtual storage bridge between the smart storage transaction manager and a LBA bus; a NVM controller, coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the host data from the virtual storage bridge; and a hybrid mapper, in the NVM controller, that maps the LBA to a physical block address (PBA), the hybrid mapper generating the PBA for block-mapped host data, and the hybrid mapper generating the PBA and a page number for host data that is page-mapped; a plurality of flash channels that include the assigned flash channel, wherein a flash channel comprises; NVM flash memory, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the hybrid mapper in the NVM controller, and at a page location identified by the page number for the page-mapped host data; whereby the hybrid mapper performs address mapping for block-mapped host data, and also performs address mapping for page-mapped host data to access the NVM flash memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A hybrid-mapped solid-state disk comprising:
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volatile memory buffer means for temporarily storing host data in a volatile memory that loses data when power is disconnected; smart storage switch means for switching host commands to a plurality of downstream devices, the smart storage switch means comprising; upstream interface means, coupled to a host, for receiving host commands to access flash memory and for receiving host data and a host address; smart storage transaction manager means for managing transactions from the host; virtual storage processor means for translating the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor means performing a first level of mapping; virtual storage bridge means for transferring host data and the LBA between the smart storage transaction manager means and a LBA bus; data striping means for dividing the host data into data segments that are assigned to different ones of the plurality of flash channels; a plurality of flash channels that include the assigned flash channel, wherein a flash channel comprises; lower-level controller means for controlling flash operations, coupled to the LBA bus to receive the LBA generated by the virtual storage processor means and the host data from the virtual storage bridge means; hybrid mapper means, coupled to the lower-level controller means, for mapping the LBA to a physical block address (PBA); first-level mapping table means, accessed by the hybrid mapper means, for storing entries that store the PBA for block-mapped host data, and that store a virtual pointer when the host data is page-mapped; second-level mapping table means, accessed by the hybrid mapper means, and located by the virtual pointer read from entries in the first-level mapping table means, for storing second entries that store the PBA and a page number for host data that is page-mapped; NVM flash memory means, coupled to the lower-level controller means, for storing the block-mapped host data at a block location identified by the PBA stored by the first-level mapping table means, and for storing the page-mapped host data at a page location identified by the PBA and the page number stored by the second-level mapping table means; wherein the NVM flash memory means in the plurality of flash channels are non-volatile memory that retain data when power is disconnected, whereby address mapping is performed at two levels for page-mode host data and at one level for block-mode host data to access the NVM flash memory means. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A multi-level-controller device comprising:
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a smart storage switch which comprises; an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address; a smart storage transaction manager that manages transactions from the host; a virtual storage processor that maps the host address to an assigned flash module to generate a logical block address (LBA), the virtual storage processor performing a mapping for data striping; a virtual storage bridge between the smart storage transaction manager and a LBA bus; a volatile memory buffer for temporarily storing the host data in a volatile memory that loses data when power is disconnected; wherein the volatile memory buffer operates as a write-through cache, a write-back cache, or a read-ahead cache; a NVM controller, coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the host data from the virtual storage bridge; a logical to physical address mapper, in the NVM controller, that maps the LBA to a physical block address (PBA); a plurality of NVM devices (NVMD) that include the assigned NVMD, wherein a NVMD comprises; raw-NAND flash memory chips, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the logical to physical mapper in the NVM controller; whereby address mapping is performed to access the raw-NAND flash memory chips.
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18. A logical-block-address (LBA) flash module comprising:
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a substrate having wiring traces printed thereon, the wiring traces for conducting signals; a plurality of metal contact pads along a first edge of the substrate, the plurality of contact pads for mating with a memory module socket on a board; a plurality of Non-Volatile-Memory Devices (NVMD) mounted on the substrate for storing host data; wherein the plurality of NVMD retain data when power is disconnected to the flash module; a logical-block-address LBA bus formed by wiring traces on the substrate that connect to the plurality of metal contact pads; wherein the plurality of NVMD are coupled by the LBA bus; wherein the plurality of NVMD store host data sent over the plurality of metal pads at a block location identified by the LBA from the Host; wherein the flash module connects the plurality of NVMD to the board through the LBA bus.
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19. A logical-block-address (LBA) flash module comprising:
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a substrate having wiring traces printed thereon, the wiring traces for conducting signals; a plurality of metal contact pads along a first edge of the substrate, the plurality of contact pads for mating with a memory module socket on a board; a plurality of Non-Volatile-Memory Devices (NVMD) mounted on the substrate for storing host data from a host; wherein the plurality of NVMD retain data when power is disconnected to the flash module; a logical-block-address LBA bus formed by wiring traces on the substrate that connect to the plurality of metal contact pads; a Smart Switch Storage (SSS) Controller, mounted on the substrate, coupled to the LBA bus to receive a LBA from the board through the plurality of metal contact pads; wherein the plurality of NVMD are coupled by the LBA bus to the SSS controller; wherein the plurality of NVMD store host data sent over the plurality of metal pads at a block location identified by the LBA generated by the SSS controller.
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Specification