System and Method to Use Cache that is Embedded in a Memory Hub to Replace Failed Memory Cells in a Memory Subsystem

• US 20090193290A1
• Filed: 01/24/2008
• Published: 07/30/2009
• Est. Priority Date: 01/24/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gower, Kevin C., Arimilli, Ravi K., Maule, Warren E.
• Granted Patent: US 7,770,077 B2
• Time in Patent Office: Days
• US Class Current: 714/6.32
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A memory system, data processing system, and method are provided for using cache that is embedded in a memory hub device to replace failed memory cells. A memory module comprises an integrated memory hub device. The memory hub device comprises an integrated memory device data interface that communicates with a set of memory devices coupled to the memory hub device and a cache integrated in the memory hub device. The memory hub device also comprises an integrated memory hub controller that controls the data that is read or written by the memory device data interface to the cache based on a determination whether one or more memory cells within the set of memory devices has failed.

Claims

1. A memory system comprising:

a memory hub device integrated in a memory module;

a memory device data interface integrated in the memory hub device that communicates with a set of memory devices coupled to the memory hub device and a cache integrated in the memory hub device; and

a memory hub controller integrated in the memory hub device, wherein the memory hub controller controls the data that is read or written by the memory device data interface to the cache based on a determination whether one or more memory cells within the set of memory devices has failed.

2. The memory system of claim 1, wherein determining whether one or more memory cells within the set of memory devices have failed comprises:

detecting an error in read data that is read from the one or more memory cells;

correcting the error in the read data thereby forming corrected data;

writing the corrected data to the one or more memory cells;

rereading the corrected data from the one or more memory cells;

determining if the error still exists within the corrected data; and

responsive to a persistence of the error in the corrected data, indicating the one or more memory cells as failed.

3. The memory system of claim 2, further comprising:

responsive to an absence of the error in the corrected data, recording the error as a transient error.

4. The memory system of claim 1, wherein the cache is at least one of content addressable cache or address mapped cache.

5. The memory system of claim 1, wherein the memory hub device further comprises:

a link interface, coupled to the memory device data interface and the memory hub controller, that provides a communication path between the memory module and an external memory controller, and wherein the memory hub controller controls the transfer of data between the memory device data interface and the link interface.

6. The memory system of claim 5, wherein the memory hub device further comprises:

a first multiplexer coupled to the link interface and a second multiplexer in the memory device data interface; and

a read data queue coupled to the first multiplexer and the second multiplexer in the memory device data interface, wherein the memory hub controller controls the transfer of data between the second multiplexer and the link interface by sending one or more control signals to the first multiplexer to select either a direct input from the second multiplexer or an input from the read data queue for output by the first multiplexer to the link interface.

7. The memory system of claim 6, wherein the memory hub controller controls the transfer of data between at least one of the set of memory devices or the cache to the first multiplexer by sending one or more control signals to the second multiplexer to select either data from the set of memory devices or the data from the cache.

8. The memory system of claim 7, wherein the memory hub controller sends a control signal to the second multiplexer to select the input from the cache or the set of memory devices based on an address of the data.

9. The memory system of claim 6, wherein the memory hub controller sends a control signal to the first multiplexer to select the input from the read data queue based on a state of the read data queue and a state of the link interface.

10. The memory system of claim 1, wherein the memory module is one of a dual in-line memory module (DIMM) or a single in-line memory module (SIMM).

11. The memory system of claim 1, wherein the memory module is part of a data processing device.

12. The memory system of claim 1, wherein the memory module is part of a main memory of a data processing system.

13. A data processing system, comprising:

a processor; and

a memory coupled to the processor, wherein the memory comprises one or more memory modules, each memory module comprising;

a memory hub device integrated in the memory module;

a memory device data interface integrated in the memory hub device that communicates with a set of memory devices coupled to the memory hub device and a cache integrated in the memory hub device; and

a memory hub controller integrated in the memory hub device, wherein the memory hub controller controls the data that is read or written by the memory device data interface to the cache based on a determination whether one or more memory cells within the set of memory devices has failed.

14. The data processing system of claim 13, wherein determining whether the one or more memory cells within the set of memory devices have failed comprises the processor executing instructions stored in the memory that cause the processor to:

detect an error in read data that is read from the one or more memory cells;

correct the error in the read data thereby forming corrected data;

write the corrected data to the one or more memory cells;

reread the corrected data from the one or more memory cells;

determine if the error still exists within the corrected data; and

responsive to a persistence of the error in the corrected data, indicate the one or more memory cells as failed.

15. The data processing system of claim 14, wherein the instructions further cause the processor to:

responsive to an absence of the error in the corrected data, record the first error as a transient error.

16. The data processing system of claim 13, wherein the cache is at least one of content addressable cache or address mapped cache.

17. A method for using cache that is embedded in a memory hub device to replace failed memory cells, comprising:

receiving, in the memory hub device integrated in the memory module, an access request for accessing a set of memory devices of the memory module coupled to the memory hub device and a cache integrated in the memory hub device;

transferring data between a memory device data interface of the memory hub device and at least one of the set of memory devices or the cache; and

controlling, by a memory hub controller integrated in the memory hub device, the data that is read or written by the memory device data interface to the cache based on a determination whether one or more memory cells within the set of memory devices has failed.

18. The method claim 17, wherein determining whether one or more memory cells within the set of memory devices have failed comprises:

detecting an error in read data that is read from the one or more memory cells;

correcting the error in the read data thereby forming corrected data;

writing the corrected data to the one or more memory cells;

rereading the corrected data from the one or more memory cells;

determining if the error still exists within the corrected data; and

responsive to a persistence of the error in the corrected data, indicating the one or more memory cells as failed.

19. The method of claim 18, further comprising:

responsive to an absence of the error in the corrected data, recording the first error as a transient error.

20. The method of claim 17, wherein the cache is at least one of content addressable cache or address mapped cache.