Method and Apparatus for Testing a Full System Integrated Circuit Design by Statistical Fault Injection Using Hardware-Based Simulation

• US 20090193296A1
• Filed: 01/30/2008
• Published: 07/30/2009
• Est. Priority Date: 01/30/2008
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Kudva, Prabhakar Nandavar, Schumann, John Andrew, Sanda, Naoko Pia, Kellington, Jeffrey William
• Granted Patent: US 8,073,668 B2
• Time in Patent Office: Days
• US Class Current: 714/33
• CPC Class Codes: G01R 31/31816 Soft error testing; Soft error rate evaluation; Single event testing
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation

Abstract

A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator simulator thus emulates the full system IC model. Of all possible fault injection points in the model, the test manager IHS selects a subset of those injection points for fault injection via a statistical sampling method in one embodiment. In response to commands from the test manager IHS, the simulator serially injects faults into the selected fault injection points. The test manager IHS stores results for respective fault injections at the selected injection points. If a machine checkstop or silent data corruption error occurs as a result of an injected fault, the DUT IC model may return to a stored checkpoint and resume operation from the stored checkpoint. The result information is useful in determining a soft error rate (SER) for the DUT IC.

Claims

1. An integrated circuit (IC) test system, comprising:

a test manager information handling system (IHS) that includes a system memory that stores a full system model for a device under test integrated circuit (DUT IC), the full system model including a support memory;

a hardware accelerator simulator, coupled to the test manager IHS via an interface bus, the hardware accelerator simulator including a hardware accelerator memory;

the test manager IHS being configured to transmit the full system model to the hardware accelerator simulator;

the hardware accelerator simulator being configured to map the full system model to the hardware accelerator memory so that the hardware accelerator simulator emulates the full system model, thus providing a mapped hardware accelerator simulator that emulates the DUT IC as an emulated DUT IC and emulates the support memory as an emulated memory, the full system model including a plurality of fault injection points;

the test manager IHS being configured to load an architecture verification program (AVP) into the emulated memory, the AVP being capable of testing the full system model for results of injected faults, and to select a subset of the plurality of fault injection points for fault injection, thus providing a plurality of selected fault injection points; and

the mapped hardware accelerator simulator being further configured to inject a fault into a selected fault injection point of the plurality of selected fault injection points in the full system model when commanded by the test manager IHS, and to transmit to the test manager IHS for storage a result of injecting the fault into the selected injection point, the mapped hardware accelerator simulator being further configured to inject faults at other selected fault injection points to provide respective results.

2. The IC test system of claim 1, wherein the full system model includes a first model for the DUT IC and a second model for at least one supporting IC that operates cooperatively with the DUT IC, the at least one supporting IC of the second model including the support memory.

3. The IC test system of claim 1, wherein the full system model represents a system on a chip (SOC).

4. The IC test system of claim 1, wherein the test manager selects the subset of the plurality of injection points by random selection.

5. The IC test system of claim 1, wherein the test manager selects the subset of the plurality of injection points by statistical sampling.

6. The IC test system of claim 1, wherein the injection points of the full system model correspond to non array latches.

7. The IC test system of claim 1, wherein the test manager is configured to store results from the mapped hardware accelerator simulator.

8. The IC test system of claim 1, wherein the test manager IHS includes the AVP, the test manager IHS being configured to transmit the AVP to the emulated memory in the hardware accelerator simulator via the interface bus.

9. The IC test system of claim 1, wherein the AVP is configured to highly utilize the DUT full system model and to detect silent data corruption errors and checkstops in the DUT full system model that result from injected faults.

10. A method of testing an integrated circuit (IC), the method comprising:

transmitting, by a test manager information handling system (IHS) to a hardware accelerator simulator, a full system model for a device under test integrated circuit (DUT IC), the full system model including a support memory;

mapping, by the hardware accelerator simulator, the full system model into a hardware accelerator memory of the hardware accelerator simulator so that the hardware accelerator simulator emulates the full system model, thus providing a mapped hardware accelerator simulator that emulates the DUT IC as an emulated DUT IC and emulates the support memory as an emulated memory, the full system model including a plurality of fault injection points;

loading, by the test manager IHS, an architecture verification program (AVP) into the emulated memory, the AVP being capable of testing the full system model for results of injected faults;

selecting, by the test manager IHS, a subset of the plurality of fault injection points for fault injection, thus providing a plurality of selected fault injection points;

injecting a fault, by the mapped hardware accelerator simulator as commanded by the test manager IHS, into a selected fault injection point of the plurality of selected fault injection points in the full system model;

storing, by the test manager IHS, a result of the fault injection of the injecting step, the result being detected by the AVP; and

repeating the injecting and storing steps for other selected fault injection points to collect respective results for fault injections at respective fault injection points.

11. The method of claim 10, wherein the full system model includes a first model for the DUT IC and a second model for at least one supporting IC that operates cooperatively with the DUT IC, the at least one supporting IC of the second model including the support memory.

12. The method of claim 10 wherein the selecting step selects the subset of the plurality of injection points by random selection.

13. The method of claim 10, wherein the selecting step selects the subset of the plurality of injection points by a statistical sampling method.

14. The method of claim 10, wherein the injection points of the full system model correspond to non array latches.

15. The method of claim 10, wherein the injecting step and storing step inject a fault and store a result one fault injection at a time.

16. The method of claim 10, further comprising determining a soft error rate (SER) for the full system model from the fault injection results.

17. The method of claim 10, further comprising transmitting, by the test manager IHS, the AVP from the test manager IHS to the mapped hardware accelerator simulator.

18. The method of claim 10, wherein the AVP is configured to highly utilize the DUT full system model and to detect silent data corruption errors and checkstops in the DUT full system model that result from injected faults.

19. A computer program product stored on a computer operable medium, comprising:

instructions that store a full system model for a device under test integrated circuit (DUT IC), the full system model including a support memory;

instructions that map the full system model into a hardware accelerator simulator that emulates the full system model, thus providing a mapped hardware accelerator simulator that emulates the DUT IC as an emulated DUT IC and emulates the support memory as an emulated memory, the full system model including a plurality of fault injection points;

instructions that load an architecture verification program (AVP) into the emulated memory, the AVP being capable of testing the full system model for results of injected faults;

instructions that select a subset of the plurality of fault injection points for fault injection, thus providing a plurality of selected fault injection points;

instructions that inject a fault into a selected fault injection point of the plurality of selected fault injection points in the full system model;

instructions that store a result of the fault injection, the result being detected by the AVP; and

instructions that repeat the injecting a fault and storing a result for other selected fault injection points to collect respective results for fault injections at respective fault injection points.

20. The computer program product of claim 19, wherein the instructions that select a subset of the plurality of fault injection points for fault injection employ random selection to select the injection points.

21. The computer program product of claim 19, wherein instructions that select a subset of the plurality of fault injection points for fault injection employ statistical sampling to select the injection points.