System for a Combined Error Correction Code and Cyclic Redundancy Check Code for a Memory Channel

• US 20090193315A1
• Filed: 01/24/2008
• Published: 07/30/2009
• Est. Priority Date: 01/24/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gower, Kevin C., Maule, Warren E.
• Granted Patent: US 8,140,936 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Abstract

A memory system is provided that performs error correction at a memory device level. The memory system comprises a memory hub device integrated in the memory module and a link interface integrated in the memory hub device that provides a communication pathway between the memory hub device and an external memory controller. The link interface comprises first error correction logic integrated in the link interface that performs error correction operations on first data that is received from the external memory controller via a first memory channel to be transmitted to a set of memory devices. The first error correction logic generates a first error signal to the external memory controller in response to the first error correction logic detecting a first error in the first data. Link interface control logic integrated in the link interface controls the transmission of the first data to the set of memory devices.

Claims

1. A memory system comprising:

a memory hub device integrated in a memory module; and

a link interface integrated in the memory hub device that provides a communication pathway between the memory hub device and an external memory controller, wherein the link interface comprises;

first error correction logic integrated in the link interface, wherein the first error correction logic performs error correction operations on first data that is received from the external memory controller via a first memory channel to be transmitted to a set of memory devices and wherein the first error correction logic generates a first error signal to the external memory controller in response to the first error correction logic detecting a first error in the first data; and

link interface control logic integrated in the link interface, wherein the link interface control logic controls the transmission of the first data to the set of memory devices.

2. The memory system of claim 1, wherein the link interface further comprises:

second error correction logic integrated in the link interface,

wherein the second error correction logic performs error correction operations on second data that is received from at least one of an additional memory hub device or standalone repeater hub device via a second memory channel to be transmitted to the external memory controller,

wherein the second error correction logic generates a second error signal to the external memory controller in response to the second error correction logic detecting the second error in the second data, and

wherein the link interface control logic controls the transmission of the second data to the external memory controller.

3. The memory system of claim 1, wherein the link interface further comprises:

first error logic generation integrated in the link interface,

wherein the first error logic generation generates error correcting code bits on second data that is received from the memory hub device to be transmitted to the external memory controller, and

wherein the link interface control logic controls the transmission of the second data to the set of memory devices.

4. The memory system of claim 1, wherein the link interface sends the first data to a multiplexer and wherein the link interface control logic signals the multiplexer to transmit the first data from receive logic in response to the first error correction logic failing to detect the first error in the first data.

5. The memory system of claim 1, wherein the link interface sends the first data to a multiplexer and wherein the link interface control logic signals the multiplexer to transmit the first error signal in response to the first error correction logic detecting the first error in the first data.

6. The memory system of claim 1, wherein the first error correction logic checks the first data from the external memory controller for errors using error code bits prior to transmitting the first data to the set of memory devices.

7. The memory system of claim 2, wherein the second error correction logic checks the second data from the at least one of the additional memory hub device or the standalone repeater hub device for errors using error code bits prior to transmitting the second data to the external memory controller via the first memory channel.

8. The memory system of claim 5, wherein the link interface sends the second data to the multiplexer prior to transmitting the second data to the external memory controller and wherein the link interface control logic signals the multiplexer to transmit the second data to the external memory controller along with the second error signal from the second error correction logic in response to the second error correction logic detecting the second error in the second data.

9. The memory system of claim 5, wherein the link interface sends the second data to the multiplexer prior to transmitting the second data to the external memory controller and wherein the link interface control logic signals the multiplexer to transmit the second data to the external memory controller in response to the second error correction logic failing to detect the second error in the second data.

10. The memory system of claim 3, wherein the first error logic generation generates an error correction codeword that is added to the second data before transmitting the second data to the external memory controller via the first memory channel.

11. The memory system of claim 1, wherein the memory module is one of a dual in-line memory module (DIMM) or a single in-line memory module (SIMM).

12. The memory system of claim 1, wherein the memory module is part of a data processing device.

13. A data processing system, comprising:

a processor; and

a memory coupled to the processor, wherein the memory comprises one or more memory modules, each memory module comprising;

a memory hub device integrated in the memory module; and

a link interface integrated in the memory hub device that provides a communication pathway between the memory hub device and an external memory controller, wherein the link interface comprises;

first error correction logic integrated in the link interface, wherein the first error correction logic performs error correction operations on first data that is received from the external memory controller via a first memory channel to be transmitted to a set of memory devices and wherein the first error correction logic generates a first error signal to the external memory controller in response to the first error correction logic detecting a first error in the first data; and

link interface control logic integrated in the link interface, wherein the link interface control logic controls the transmission of the first data to the set of memory devices.

14. The data processing system of claim 13, wherein the link interface further comprises:

second error correction logic integrated in the link interface,

wherein the second error correction logic performs error correction operations on second data that is received from at least one of an additional memory hub device or standalone repeater hub device via a second memory channel to be transmitted to the external memory controller,

wherein the second error correction logic generates a second error signal to the external memory controller in response to the second error correction logic detecting the second error in the second data, and

wherein the link interface control logic controls the transmission of the second data to the external memory controller.

15. The data processing system of claim 13, wherein the link interface further comprises:

first error logic generation integrated in the link interface,

wherein the first error logic generation generates error correcting code bits on second data that is received from the memory hub device to be transmitted to the external memory controller, and

wherein the link interface control logic controls the transmission of the second data to the set of memory devices.

16. The data processing system of claim 13, wherein the link interface sends the first data to a multiplexer and wherein the link interface control logic signals the multiplexer to transmit the first data from receive logic in response to the first error correction logic failing to detect the first error in the first data.

17. The data processing system of claim 13, wherein the link interface sends the first data to a multiplexer and wherein the link interface control logic signals the multiplexer to transmit the first error signal in response to the first error correction logic detecting the first error in the first data.

18. The data processing system of claim 13, wherein the first error correction logic checks the first data from the external memory controller for errors using error code bits prior to transmitting the first data to the set of memory devices.

19. The data processing system of claim 14, wherein the second error correction logic checks the second data from the at least one of the additional memory hub device or the standalone repeater hub device for errors using error code bits prior to transmitting the second data to the external memory controller via the first memory channel.

20. A method for performing error correction operations in a memory module, comprising:

receiving, by a link interface in a memory hub device integrated in the memory module, an access request for accessing a set of memory devices of the memory module coupled to the memory hub device; and

performing, by error correction logic integrated in the link interface, one or more error correction operations on data that is to be transmitted to the set of memory devices,

wherein the error correction logic performs the one or more error correction operations on the data that is received from an external memory controller via a memory channel to be transmitted to the set of memory devices,

wherein the error correction logic generates an error signal to the memory controller in response to the error correction logic detecting an error in the data, and

wherein link interface control logic integrated in the link interface controls the transmission of the data to the set of memory devices.