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System for a Combined Error Correction Code and Cyclic Redundancy Check Code for a Memory Channel

  • US 20090193315A1
  • Filed: 01/24/2008
  • Published: 07/30/2009
  • Est. Priority Date: 01/24/2008
  • Status: Active Grant
First Claim
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1. A memory system comprising:

  • a memory hub device integrated in a memory module; and

    a link interface integrated in the memory hub device that provides a communication pathway between the memory hub device and an external memory controller, wherein the link interface comprises;

    first error correction logic integrated in the link interface, wherein the first error correction logic performs error correction operations on first data that is received from the external memory controller via a first memory channel to be transmitted to a set of memory devices and wherein the first error correction logic generates a first error signal to the external memory controller in response to the first error correction logic detecting a first error in the first data; and

    link interface control logic integrated in the link interface, wherein the link interface control logic controls the transmission of the first data to the set of memory devices.

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