Vertical system integration

• US 20090194768A1
• Filed: 04/02/2009
• Published: 08/06/2009
• Est. Priority Date: 08/08/2002
• Status: Abandoned Application

• Current Assignee: Glenn J. Leedy
• Original Assignee: Glenn J. Leedy
• Inventors: Leedy, Glenn J.
• Application Number:
  US12/417,022
• Publication Number:
  US 20090194768A1
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: B81B 7/02 containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] B81B7/04 takes precedence
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/52 Arrangements for conducting electric current within the device in operation from one component to another , i.e. interconnections, e.g. wires, lead frames optical interconnections G02B6/00
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/118 : Masterslice integrated circuits
• CPC Class Codes: H01L 27/11803 : using field effect technology
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1463 : Pixel isolation structures
• CPC Class Codes: H01L 27/14643 : Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14683 : Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 29/40114 : the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 : the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42324 : Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 : with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 : with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/78648 : arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04W 4/80 : Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/30 : DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

Claims

1. A first stacked integrated circuit related to a second stacked integrated circuit, the first stacked integrated circuit comprising:

a plurality of integrated circuits held in an unmovable relation to one another, including a plurality of integrated circuits of at least one integrated circuit type;

wherein the second stacked integrated circuit comprises at least one integrated circuit of said integrated circuit type, and said first stacked integrated circuit comprising at least one more integrated circuit of said integrated circuit type than said second stacked integrated circuit, the integrated circuits of said integrated circuit type within the first stacked integrated circuit being of substantially the same design as the integrated circuits of said integrated circuit type within the second stacked integrated circuit.

2. The apparatus of claim 1, wherein the integrated circuits of said integrated circuit type within the first stacked integrated circuit being of identical design as the integrated circuits of said integrated circuit type within the second stacked integrated circuit.

3. The apparatus of claim 1, wherein at least one of the integrated circuits of the first stacked integrated circuit comprises reconfiguration circuitry.

4. The apparatus of claim 1, wherein at least one of the plurality of integrated circuits of the first stacked integrated circuit provides at least one of redundant logic circuitry and redundant memory locations.

5. The apparatus of claim 1, further comprising test circuitry in at least one of the integrated circuits of the first stacked integrated circuit, wherein the test circuitry provides at least one of circuit testing before the first stacked integrated circuit is completed and after the first stacked integrated circuit is completed.

6. The apparatus of claim 1, wherein at least one of the integrated circuits of the first stacked integrated circuit has a thickness of less than 50 microns.

7. The apparatus of claim 1, wherein at least one of the integrated circuits of the first stacked integrated circuit is a thinned substantially flexible integrated circuit, formed with a low stress dielectric, wherein the low stress dielectric is at least one of an oxide of silicon and a nitride of silicon and is caused to have a tensile stress of about 5×

10⁸ dynes/cm² or less.

8. The apparatus of claim 1, wherein at least two of the plurality of integrated circuits of the first stacked integrated circuit are bonded together by means of a patterned metal bond layer.

9. The apparatus of claim 1, wherein the plurality of integrated circuits of the first stacked integrated circuit comprise means for performing a plurality of uniquely initiated concurrent information transfers on distinct transmission paths.

10. The apparatus of claim 1, further comprising vertical interconnects interconnecting a plurality of integrated circuits of the first stacked integrated circuit, the vertical interconnects comprising vertical interconnect segments formed of a first metal contact on a first substrate bonded to a second aligned metal contact on a second adjacent substrate.

11. The apparatus of claim 1, further comprising a substantially rigid substrate supporting at least one of the plurality of integrated circuits of the first stacked integrated circuit, the substantially rigid substrate having a first thickness, wherein at least one of the integrated circuits of the first stacked integrated circuit has a second thickness, wherein the second thickness is substantially less than the first thickness.

12. The apparatus of claim 1, wherein at least one of the integrated circuits of the first stacked integrated circuit is fabricated with at least one of a different semiconductor process technology and a different geometric process fabrication technology than at least one of the other integrated circuits of the first stacked integrated circuit.

13. A first stacked integrated circuit related to a second stacked integrated circuit, the first stacked integrated circuit comprising:

a plurality of integrated circuits held in an unmovable relation to one another, including a plurality of memory integrated circuits of at least one integrated circuit type;

wherein the second stacked integrated circuit comprises at least one memory integrated circuit of said integrated circuit type, and said first stacked integrated circuit comprising at least one more memory integrated circuit of said integrated circuit type than said second stacked integrated circuit, the memory integrated circuits of said integrated circuit type within the first stacked integrated circuit being of substantially the same design as the memory integrated circuits of said integrated circuit type within the second stacked integrated circuit.

14. The apparatus of claim 13, wherein the integrated circuits of said integrated circuit type within the first stacked integrated circuit being of identical design as the integrated circuits of said integrated circuit type within the second stacked integrated circuit.

15. A first stacked integrated circuit related to a second stacked integrated circuit, the first stacked integrated circuit comprising:

a plurality of integrated circuits held in an unmovable relation to one another, including a plurality of integrated circuits of at least one integrated circuit type;

wherein the second stacked integrated circuit comprises at least one integrated circuit of said integrated circuit type, and said first stacked integrated circuit comprising at least one more integrated circuit of said integrated circuit type than said second stacked integrated circuit, wherein a design of the integrated circuits of said integrated circuit type within the first stacked integrated circuit and a design of the integrated circuits of said integrated circuit type within the second stacked integrated circuit are the same or are derived from the same integrated circuit design.

16. A first stacked integrated circuit related to a second stacked integrated circuit, the first stacked integrated circuit comprising:

a plurality of integrated circuits held in an unmovable relation to one another, including a plurality of integrated circuits of at least one integrated circuit type;

wherein the second stacked integrated circuit comprises at least one memory integrated circuit of said integrated circuit type, and said first stacked integrated circuit comprising at least one more integrated circuit of said integrated circuit type than said second stacked integrated circuit, wherein a design of the memory integrated circuits of said integrated circuit type within the first stacked integrated circuit and a design of the memory integrated circuits of said integrated circuit type within the second stacked integrated circuit are the same or are derived from the same integrated circuit design.

17. A first stacked integrated circuit related to a second stacked integrated circuit, the first stacked integrated circuit comprising:

a plurality of integrated circuits held in an unmovable relation to one another, including a plurality of integrated circuits of at least one integrated circuit type;

wherein the second stacked integrated circuit comprises at least one integrated circuit of said integrated circuit type, and said first stacked integrated circuit comprising at least one more integrated circuit of said integrated circuit type than said second stacked integrated circuit, the integrated circuits of said integrated circuit type within the first stacked integrated circuit being functionally equivalent to the integrated circuits of said integrated circuit type within the second stacked integrated circuit.

18. A first stacked integrated circuit related to a second stacked integrated circuit, the first stacked integrated circuit comprising:

a plurality of integrated circuits held in an unmovable relation to one another, including a plurality of memory integrated circuits of at least one integrated circuit type;

wherein the second stacked integrated circuit comprises at least one memory integrated circuit of said integrated circuit type, and said first stacked integrated circuit comprising at least one more memory integrated circuit of said integrated circuit type than said second stacked integrated circuit, the memory integrated circuits of said integrated circuit type within the first stacked integrated circuit being functionally equivalent to the memory integrated circuits of said integrated circuit type within the second stacked integrated circuit.

19. A first stacked integrated circuit related to a second stacked integrated circuit, the first stacked integrated circuit comprising:

a plurality of integrated circuits held in an unmovable relation to one another, including a plurality of integrated circuits of at least one integrated circuit type;

wherein the second stacked integrated circuit comprises at least one integrated circuit of said integrated circuit type, and said first stacked integrated circuit comprising at least one more integrated circuit of said integrated circuit type than said second stacked integrated circuit.

20. A first stacked integrated circuit related to a second stacked integrated circuit, the first stacked integrated circuit comprising:

a plurality of integrated circuits held in an unmovable relation to one another, including a plurality of memory integrated circuits of at least one integrated circuit type;

wherein the second stacked integrated circuit comprises at least one memory integrated circuit of said integrated circuit type, and said first stacked integrated circuit comprising at least one more memory integrated circuit of said integrated circuit type than said second stacked integrated circuit.