SEMICONDUCTOR DEVICE USING ELEMENT ISOLATION REGION OF TRENCH ISOLATION STRUCTURE AND MANUFACTURING METHOD THEREOF

• US 20090194810A1
• Filed: 01/28/2009
• Published: 08/06/2009
• Est. Priority Date: 01/31/2008
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kubota, Hiroshi, KIYOTOSHI, Masahiro
• Application Number:
  US12/361,340
• Publication Number:
  US 20090194810A1
• Time in Patent Office: Days
• US Class Current: 257/326
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A stacked film including a gate dielectric film and electrode film of each memory cell of a flash memory is formed on a semiconductor substrate. The stacked film is patterned by reactive ion etching to form an isolation trench for formation of an element isolation region and the surface of the semiconductor substrate is exposed to the internal portion of the isolation trench. An O₃-TEOS film exhibiting underlying material selectivity during the deposition is formed in the isolation trench as the first filling dielectric film and then the isolation trench is filled with the second filling dielectric film to form an element isolation region of an STI structure.

Claims

1. A manufacturing method of a semiconductor device comprising:

forming a stacked film configuring a semiconductor device on a semiconductor substrate,

patterning the stacked film by reactive ion etching to form an isolation trench that isolates elements and expose a surface of the semiconductor substrate at least a bottom portion of the isolation trench,

filling an O₃-TEOS series film exhibiting underlying material selectivity as a first filling dielectric film in the isolation trench to have a thick film thickness on the bottom portion of the isolation trench, and

filling the isolation trench with a second filling dielectric film to form an element-element isolation region.

2. The manufacturing method of the semiconductor device according to claim 1, wherein the second filling dielectric film includes one of an O₃-TEOS series film having a smaller underlying material selectivity than the O₃-TEOS series film during the film deposition, a silicon oxide film deposited by a high-density plasma-CVD method and an SOG film.

3. The manufacturing method of the semiconductor device according to claim 1, further comprising forming one of a polysilicon film, amorphous silicon film and silicon germanium film acting as a stopper in a chemical mechanical polishing process as part of the stacked film configuring the semiconductor device.

4. The manufacturing method of the semiconductor device according to claim 1, further comprising oxidizing an internal surface of the isolation trench over the first filling dielectric film after forming the O₃-TEOS series film that is the first filling dielectric film and before filling the isolation trench with the second filling dielectric film.

5. The manufacturing method of the semiconductor device according to claim 1, wherein the forming the O₃-TEOS series film is performed while pure water is being introduced into a process chamber.

6. The manufacturing method of the semiconductor device according to claim 1, in which the stacked film includes a third dielectric film used as gate dielectric films of memory cells and a first conductive film used as charge storage layers and which further comprises forming a fourth dielectric film on the first conductive film, forming a second conductive film on the third dielectric film, patterning the second conductive film and fourth dielectric film to form word lines and charge storage layers that partially act as the control gates, exposing a surface of the semiconductor substrate on an active area in portions between the adjacent word lines, filling an O₃-TEOS film exhibiting underlying material selectivity during the film deposition as the first dielectric film on the exposed surface of the semiconductor substrate in the portions between the adjacent word lines, and filling the second dielectric film on the first dielectric film to fill the portions between the adjacent word lines.

7. The manufacturing method of the semiconductor device according to claim 6, wherein the exposing the surface of the semiconductor substrate is exposing the surface of the semiconductor substrate by further advancing the etching to remove the third dielectric film when the second conductive film, fourth dielectric film and first conductive film are patterned by the etching process.

8. The manufacturing method of the semiconductor device according to claim 6, further comprising oxidizing side surfaces of the word lines and charge storage layers through the fourth dielectric film after filling the first dielectric film into the portions between the adjacent word lines.

9. The manufacturing method of the semiconductor device according to claim 6, wherein the exposing the surface of the semiconductor substrate is performed by patterning the second conductive film, fourth dielectric film and first conductive film by the etching process and eliminating a silicon oxide film formed on the surface of the semiconductor substrate on the active area by further performing the etching process after post oxidation.

10. The manufacturing method of the semiconductor device according to claim 6, wherein the forming the O₃-TEOS series film is performed while pure water is being introduced into a process chamber.

11. A semiconductor device comprising:

an active area formed on a semiconductor substrate, and

a shallow trench isolation portion having an isolation trench formed to separate the active area from an adjacent active area and a dielectric film filled in the isolation trench,

wherein the dielectric film filled in the isolation trench is a stacked film having a first dielectric film formed of an O₃-TEOS series film filled to have a thick film thickness on a bottom portion of the isolation trench and a second dielectric film formed on the first dielectric film.

12. The semiconductor device according to claim 11, wherein the active area includes a memory cell portion having elements isolated by a first isolation trench and a peripheral circuit portion having elements isolated by a second isolation trench having wider width than the first isolation trench, and an O₃-TEOS series film that is the first dielectric film is filled to have a thicker film thickness on corners of the bottom portion of the second isolation trench.

13. The semiconductor device according to claim 11, wherein the first isolation trench is substantially filled with an O₃-TEOS series film that is the first dielectric film.

14. The semiconductor device according to claim 11, wherein an O₃-TEOS series film that is the second dielectric film filled in the second isolation trench is formed to have not higher than 1:

1.5 in a film thickness ratio of film portions formed on sidewalls and bottom portion of the element isolation trench and have a film thickness of not smaller than 50 nm on the bottom portion of the element isolation trench.

15. The semiconductor device according to claim 11, wherein the second dielectric film includes one of an O₃-TEOS series film, a silicon oxide film formed by a high-density plasma-CVD method and an SOG film.

16. The semiconductor device according to claim 15, wherein the SOG film is a polysilazane film.

17. A semiconductor device comprising:

memory cells each having a gate dielectric film, charge storage layer, inter-polysilicon gate dielectric film and control gate stacked on a semiconductor substrate,

an element isolation region of a trench isolation structure formed on the semiconductor substrate,

the first dielectric films formed of O₃-TEOS series films filled in portions on an active area between adjacent word lines without causing any seam,

the second dielectric films filled on the first dielectric films in the portions between adjacent word lines, and

the third dielectric films filled to surround upper portions of the element isolation region in the portions between adjacent word lines.

18. The semiconductor device according to claim 17, wherein side surfaces of the charge storage layers and word lines are oxidized.

19. The semiconductor device according to claim 17, wherein the second dielectric film includes one of an O₃-TEOS series film, a silicon oxide film formed by a high-density plasma-CVD method and an SOG film.

20. The semiconductor device according to claim 19, wherein the SOG film is a polysilazane film.