Structure and Method for Forming Field Effect Transistor with Low Resistance Channel Region

• US 20090194811A1
• Filed: 12/08/2008
• Published: 08/06/2009
• Est. Priority Date: 12/13/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Pan, James, Wang, Qi
• Granted Patent: US 7,825,465 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a first PN junction with the silicon region, and each body region includes a silicon-germanium layer of the second conductivity type laterally extending between adjacent trenches. Source regions of the first conductivity flank the trenches, and each source region forms a second PN junction with one of the body regions. Channel regions extend in the body regions along sidewalls of the trenches between the source regions and a bottom surface of the body regions. The silicon-germanium layers extend into corresponding channel regions to thereby reduce the channel resistance.

Claims

1. A trench-gate field effect transistor comprising:

trenches extending into a silicon region of a first conductivity type;

a gate electrode in each trench;

body regions of second conductivity type extending over the silicon region between adjacent trenches, each body region forming a first PN junction with the silicon region, and each body region including a silicon-germanium layer of the second conductivity type laterally extending between adjacent trenches;

a gate dielectric layer lining at least upper sidewalls of each trench, the gate dielectric layer insulating the gate electrode from the body region;

source regions of the first conductivity flanking the trenches, each source region forming a second PN junction with one of the body regions; and

channel regions extending in the body regions along sidewalls of the trenches between the source regions and a bottom surface of the body regions, wherein the silicon-germanium layers extend into corresponding channel regions to thereby reduce the channel resistance.

2. The transistor of claim 1 wherein the silicon-germanium layer is spaced a predetermined distance from the second PN junctions.

3. The transistor of claim 1 wherein the silicon-germanium layer is spaced a predetermined distance from the first and second PN junctions.

4. The transistor of claim 1 wherein the silicon-germanium layer separates an upper portion of the body region from a lower portion of the body region.

5. The transistor of claim 1 wherein each silicon-germanium layer abuts sidewalls of two adjacent trenches.

6. The transistor of claim 1 wherein each silicon-germanium layer is vertically spaced from a corresponding first PN junction by a distance in the range of 500 Å

to 1,000 Å

, and from a corresponding second PN junction by a distance in the range of 500 Å

to 1,000 Å

.

7. The transistor of claim 1 wherein each trench further includes:

a shield dielectric layer thicker than the gate dielectric lining lower sidewalls of the trench;

a shield electrode in a lower portion of the trench under the gate electrode; and

an inter-electrode dielectric layer insulating the gate and shield electrodes from one another.

8. The transistor of claim 1 wherein each trench includes a thick bottom dielectric along the trench bottom below the gate electrode.

9. An N-channel trench-gate field effect transistor comprising:

trenches extending into an N-type silicon region;

a gate electrode in each trench;

body regions of P-type conductivity extending over the silicon region between adjacent trenches, each body region including a lower silicon layer of P-type conductivity forming a first PN junction with the N-type silicon region, a silicon-germanium layer of P-type conductivity over the lower silicon layer, and an upper silicon layer of P-type conductivity over the silicon-germanium layer; and

source regions of N-type conductivity type flanking the trenches, each source region forming a second PN junction with the upper silicon layer.

10. The transistor of claim 9 wherein each silicon-germanium layer abuts sidewalls of two adjacent trenches.

11. The transistor of claim 9 wherein each silicon-germanium layer is vertically spaced from corresponding first and second PN junctions.

12. The transistor of claim 9 wherein each trench further includes:

a shield dielectric layer thicker than the gate dielectric lining lower sidewalls of the trench;

a shield electrode in a lower portion of the trench under the gate electrode; and

an inter-electrode dielectric layer insulating the gate and shield electrodes from one another.

13. The transistor of claim 9 wherein each trench includes a thick bottom dielectric along the trench bottom below the gate electrode.

14. The transistor of claim 9 further comprising channel regions extending in the body regions along sidewalls of the trenches between the source regions and a bottom surface of the body regions, wherein the silicon-germanium layers extend into corresponding channel regions to thereby reduce the channel resistance.

15. A trench-gate field effect transistor comprising:

trenches extending into a silicon region of a first conductivity type;

a gate electrode in each trench;

body regions of a second conductivity type extending over the silicon region between adjacent trenches, each body region forming a PN junction with the silicon region;

a gate dielectric layer lining at least upper sidewalls of each trench, the gate dielectric layer insulating the gate electrode from the body region;

source regions of the first conductivity flanking the trenches; and

a silicon-germanium region vertically extending through each source region and through a corresponding body region, the silicon-germanium region terminating within the corresponding body region before reaching the PN junction.

16. The transistor of claim 15 wherein each silicon-germanium region is spaced from the corresponding PN junction a distance in the range of 500 Å

to 1,000 Å

.

17. The transistor of claim 15 wherein each silicon-germanium region is bounded along its vertical boundaries by silicon regions.

18. The transistor of claim 15 wherein when the transistor is in an on state, a channel region is formed in the body region along each trench sidewall between each source region and a bottom surface of a corresponding body region, and the silicon-germanium region forms at least a part of the channel region so as to reduce the channel resistance.

19. The transistor of claim 15 wherein each trench includes silicon material insulated from the gate electrode therein.

20. The transistor of claim 15 wherein the silicon-germanium regions are disposed inside the trenches.

21. The transistor of claim 15 wherein the transistor is an P-channel transistor with the first conductivity type being P-type and the second conductivity type being N-type.

22. The transistor of claim 15 wherein each trench further includes:

a shield dielectric layer thicker than the gate dielectric lining lower sidewalls of the trench;

a shield electrode in a lower portion of the trench under the gate electrode; and

an inter-electrode dielectric layer insulating the gate and shield electrodes from one another.

23. The method of claim 15 wherein each trench includes a thick bottom dielectric along the trench bottom below the gate electrode.

24-44. -44. (canceled)