SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20090194879A1
• Filed: 12/16/2008
• Published: 08/06/2009
• Est. Priority Date: 02/01/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kato, Tatsuya, Endo, Masato
• Granted Patent: US 7,999,393 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/10 characterised by the top-view layout

Abstract

A semiconductor device includes a plurality of first interconnection layers which are provided in an insulating layer and formed in a pattern having a width and space smaller than a resolution limit of an exposure technique, and a second interconnection layer which is provided between the first interconnection layers in the insulating layer and has a width larger than that of a first interconnection layer. A space between the second interconnection layer and each of first interconnection layers adjacent to both sides of the second interconnection layer equals the space between the first interconnection layers.

Claims

1. A semiconductor device comprising:

a plurality of first interconnection layers which are provided in an insulating layer and formed in a pattern having a width and space smaller than a resolution limit of an exposure technique; and

a second interconnection layer which is provided between the first interconnection layers in the insulating layer and has a width larger than that of a first interconnection layer,

wherein a space between the second interconnection layer and each of first interconnection layers adjacent to both sides of the second interconnection layer equals the space between the first interconnection layers.

2. The device according to claim 1, wherein letting “

F”

be the width of the first interconnection layer, the width of the second interconnection layer satisfies

2 F×

n−

F (n is a natural number of not less than

     1).

3. The device according to claim 1, wherein the space equals the width of the first interconnection layer.

4. The device according to claim 1, wherein the first interconnection layers include shallow interconnections and deep interconnections which are alternately arranged.

5. The device according to claim 1, wherein the first interconnection layers and the second interconnection layer are made of one material selected from the group consisting of copper (Cu), aluminum (Al), and ruthenium (Ru).

6. The device according to claim 1, further comprising:

a cell group having a plurality of memory cells which are connected in series; and

a first select transistor and a second select transistor which are connected in series with ends of the cell group, respectively,

wherein each of the first interconnection layers is a bit line and is connected to one end of a current path of the first select transistor, and

the second interconnection layer is a shunt interconnection and is connected to one end of a current path of the second select transistor.

7. A semiconductor device comprising:

a plurality of first interconnection layers which are provided in an insulating layer and formed in a pattern having a width and space smaller than a resolution limit of an exposure technique;

two second interconnection layers each of which is provided between the first interconnection layers in the insulating layer and has a width larger than that of a first interconnection layer; and

a third interconnection layer which is provided between the second interconnection layers in the insulating layer and has a width not less than that of the first interconnection layer,

wherein a space between each of the second interconnection layers and a first interconnection layer adjacent to the second interconnection layer equals the space between the first interconnection layers, and

a space between each of the second interconnection layers and the third interconnection layer equals the space between the first interconnection layers.

8. The device according to claim 7, wherein letting “

F”

be the width of the first interconnection layer, the width of the second interconnection layer satisfies

2 F×

n−

F (n is a natural number of not less than

     1).

9. The device according to claim 7, wherein the space equals the width of the first interconnection layer.

10. The device according to claim 7, wherein the first interconnection layers include shallow interconnections and deep interconnections which are alternately arranged.

11. The device according to claim 7, wherein the first interconnection layers, the second interconnection layers and the third interconnection layer are made of one material selected from the group consisting of copper (Cu), aluminum (Al), and ruthenium (Pu).

12. The device according to claim 7, further comprising:

a cell group having a plurality of memory cells which are connected in series; and

a first select transistor and a second select transistor which are connected in series with ends of the cell group, respectively,

wherein each of the first interconnection layers is a bit line and is connected to one end of a current path of the first select transistor, and

one of the second interconnection layers is a shunt interconnection and is connected to one end of a current path of the second select transistor.

13. The device according to claim 8, wherein letting “

F”

be the width of the first interconnection layer, the width of the third interconnection layer satisfies

2 F×

m−

F (m is a natural number of not less than

     1).

14. A semiconductor device manufacturing method comprising:

forming, on an insulating layer, a plurality of first mask layers and a second mask layer which is arranged between the first mask layers and has a width larger than that of a first mask layer, the first mask layers and the second mask layer being arrayed at equal spaces;

reducing a width of each of the first mask layers and the second mask layer by selectively etching the first mask layers and the second mask layer;

forming a plurality of sidewalls on side surfaces of the first mask layers and the second mask layer;

removing the first mask layers and the second mask layer to leave the sidewalls;

selectively etching the insulating layer using the sidewalls as a mask to form, in the insulating layer, a plurality of first trenches and a second trench which is arranged between the first trenches and has a width larger than that of a first trench; and

burying a conductor in the first trenches and the second trench to form, in the insulating layer, a plurality of first interconnection layers and a second interconnection layer having a width larger than that of a first interconnection layer.

15. The method according to claim 14, wherein

each of the width and space of the first mask layers is a minimum feature size ascribable to an exposure technique, and

a width of each of the sidewalls is smaller than the minimum feature size.

16. The method according to claim 15, wherein in the step of reducing the width of each of the first mask layers and the second mask layer, letting “

2 F”

be the minimum feature size, the width of the first mask layer is reduced from “

2 F”

to “

F”

.

17. The method according to claim 15, wherein letting “

2 F”

be the minimum feature size, the width of the second mask layer satisfies

2 F×

n (n is a natural number of not less than

     1).

18. The method according to claim 15, wherein

the width of the first interconnection layer is half of the minimum feature size, and

the space between the first interconnection layers is half of the minimum feature size.

19. The method according to claim 14, wherein letting “

F”

be the width of the first interconnection layer, the width of the second interconnection layer satisfies

2 F×

n−

F (n is a natural number of not less than

     1).

20. The method according to claim 14, wherein the first mask layers and the second mask layer are made of one of silicon nitride and amorphous silicon.