INTEGRATED CIRCUIT WITH SUPPLY LINE INTRA-CHIP CLOCK INTERFACE AND METHODS FOR USE THEREWITH

• US 20090195065A1
• Filed: 01/12/2009
• Published: 08/06/2009
• Est. Priority Date: 06/21/2006
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Ahmadreza (Reza)
• Granted Patent: US 8,008,799 B2
• Time in Patent Office: Days
• US Class Current: 307/2
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01083 : Bismuth [Bi]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/19033 : being a coplanar line type
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/30111 : matching
• CPC Class Codes: H01Q 1/2283 : mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 1/38 : formed by a conductive layer on an insulating support patch antennas H01Q9/0407; microstrip dipole antennas H01Q9/065; microstrip slot antennas H01Q13/106; transmission line microstrip antennas H01Q13/206; manufacturing reflecting surfaces using insulating material for supporting the reflecting surface H01Q15/142
• CPC Class Codes: H01Q 23/00 : Antennas with active circuits or circuit elements integrated within them or attached to them
• CPC Class Codes: H01Q 9/065 : Microstrip dipole antennas patch antenna H01Q9/0407

Abstract

An integrated circuit includes a first circuit and a plurality of first power supply lines for providing a first power to the first circuit. A first intra-chip clock interface generates a first clock signal on the first power supply lines. A plurality of second power supply lines are coupled to the plurality of first power supply lines and further couple a second power to the second circuit. A second intra-chip clock interface recovers the first clock signal from the second power supply lines. The second circuit operates based on the first clock signal.

Claims

1. An integrated circuit comprising:

a first circuit;

a plurality of first power supply lines for providing a first power to the first circuit; and

a first intra-chip clock interface coupled to the first power supply lines that generates a first clock signal on the first power supply lines;

a second circuit that operates based on the first clock signal;

a plurality of second power supply lines for coupling a second power to the second circuit;

a high-pass filter for coupling the plurality of first power supply lines to the plurality of second power supply lines, wherein the high-pass filter passes the first clock signal; and

a second intra-chip clock interface coupled to the second power supply lines that recovers the first clock signal from the second power supply lines.

2. The integrated circuit of claim 1 wherein the high-pass filter includes at least one capacitive element.

3. The integrated circuit of claim 1 wherein the first clock signal is at a millimeter wave frequency.

4. The integrated circuit of claim 1 wherein the first circuit operates based on the first clock signal.

5. The integrated circuit of claim 1 wherein the first intra-chip clock interface further generates a second clock signal on the first power supply lines;

wherein the second intra-chip clock interface recovers the second clock signal from the second power supply lines; and

wherein the second circuit operates based on the second clock signal.

6. The integrated circuit of claim 5 wherein the first circuit operates based on the second clock signal.

7. The integrated circuit of claim 1 wherein the second intra-chip clock interface includes a clock generation module that generates a second clock signal based on the first clock signal.

8. The integrated circuit of claim 1 wherein the second intra-chip clock interface includes a clock generation module that generates a plurality of second clock signals based on the first clock signal.

9. An integrated circuit comprising:

a first circuit;

a plurality of first power supply lines for providing a first power to the first circuit; and

a first intra-chip clock interface coupled to the first power supply lines that generates a first clock signal on the first power supply lines;

a second circuit that operates based on the first clock signal;

a plurality of second power supply lines, coupled to the plurality of first power supply lines for coupling a second power to the second circuit; and

a second intra-chip clock interface coupled to the second power supply lines that recovers the first clock signal from the second power supply lines.

10. The integrated circuit of claim 9 wherein the plurality of first power supply lines are electrically connected to the plurality of second power supply lines.

11. The integrated circuit of claim 9 wherein the plurality of first power supply lines are coupled to the plurality of second power supply lines via a high-pass filter that passes the first clock signal.

12. The integrated circuit of claim 11 wherein the high-pass filter includes at least one capacitive element.

13. The integrated circuit of claim 9 wherein the first clock signal is at a millimeter wave frequency.

14. The integrated circuit of claim 9 wherein the first circuit operates based on the first clock signal.

15. The integrated circuit of claim 9 wherein the first intra-chip clock interface further generates a second clock signal on the first power supply lines;

wherein the second intra-chip clock interface recovers the second clock signal from the second power supply lines; and

wherein the second circuit operates based on the second clock signal.

16. The integrated circuit of claim 15 wherein the first circuit operates based on the second clock signal.

17. The integrated circuit of claim 9 wherein the second intra-chip clock interface includes a clock generation module that generates a second clock signal based on the first clock signal.

18. The integrated circuit of claim 9 wherein the second intra-chip clock interface includes a clock generation module that generates a plurality of second clock signals based on the first clock signal.

19. A method comprising:

communicating a first clock signal having a millimeter wave fundamental frequency from a first circuit to a second circuit via a plurality of power supply lines.

20. The method of claim 19 further comprising:

generating at least one second clock signal in the second circuit, based on the first clock signal.