Self-aligned phase change memory

• US 20090196091A1
• Filed: 01/31/2008
• Published: 08/06/2009
• Est. Priority Date: 01/31/2008
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kau, Derchang, Spadini, Gianpaolo, Deweerd, Wim
• Application Number:
  US12/012,107
• Publication Number:
  US 20090196091A1
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: H10B 63/24 of the Ovonic threshold switching type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/068 by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8265 on sidewalls of dielectric structures, e.g. mesa or cup type devices

Abstract

A self-aligned phase change memory may be formed by blanket depositing a number of layers and then using patterning techniques to define the individual cells. In one embodiment, a layer of phase change material may be blanket deposited over a lower electrode material. The structure may then be patterned and etched to form a plurality of spaced, parallel elongate first strips. Those strips may then be covered with a filler material, planarized, and then patterned again in a transverse direction to form a plurality of transverse, spaced, parallel second strips. The resulting structure then has singulated phase change material with connections in at least one of the row or column direction. The singulated the phase change material is self-aligned to underlying and overlying electrodes.

Claims

1. A method comprising:

patterning a structure including a lower electrode material to form a plurality of parallel, spaced first strips extending in a first direction;

planarizing said strips;

patterning the planarized first strips to form a plurality of parallel, spaced second strips extending in a second direction different than said first direction; and

forming a phase change material in one of said first or second strips.

2. The method of claim 1 including forming a stack by blanket depositing a phase change material over said lower electrode material.

3. The method of claim 2 wherein forming said stack includes blanket depositing said phase change material directly on said lower electrode material.

4. The method of claim 2 wherein patterning a structure includes patterning said stack.

5. The method of claim 2 wherein patterning a structure includes etching all the way through said stack.

6. The method of claim 5 wherein patterning the planarized first strips includes etching to form a plurality of second strips extending perpendicularly to said first direction.

7. The method of claim 6 including isotropically etching said second strips to form a necked down phase change material.

8. The method of claim 1 including forming a series of parallel, spaced elongate strips of phase change material over said lower electrode material.

9. The method of claim 8 including forming a plurality of parallel, spaced strips of material over said lower electrode material and forming sidewall spacers on said strips of said material, one of said sidewall spacers including said phase change material.

10. The method of claim 9 including forming a first sidewall spacer of a dielectric, a second sidewall spacer of a phase change material, and a third sidewall spacer of a dielectric material.

11. The method of claim 10 wherein patterning said structure includes using said sidewall spacers as a mask to pattern said structure.

12. The method of claim 11 including isotropically etching said spacer of a phase change material.

13. The method of claim 1 including forming a stack of blanket deposited layers including an ovonic threshold switch material.

14. The method of claim 13 wherein patterning a structure including a lower electrode includes etching to form a plurality of parallel, spaced first strips extending in a first direction by etching all the way through said structure.

15. The method of claim 14 including covering said first strips with a dielectric material.

16. The method of claim 15 wherein patterning the planarized first strips includes etching down to, but not through, said lower electrode material.

17. The method of claim 1 including forming singulated phase change memory material portions self-aligned to said lower electrode and an upper electrode.

18. A phase change memory comprising:

a substrate; and

a plurality of spaced, parallel elongate strips, said strips over said substrate, said strips including a plurality of spaced, singulated phase change memory material portions extending along the length of the strips, said strips including an upper electrode, over said phase change material portion, extending along the length of the strips.

19. The memory of claim 18 including a series of spaced, parallel, lower electrodes, said electrodes extending generally perpendicularly to said strips, said parallel, lower electrodes being located under said phase change memory material portions.

20. The memory of claim 18 wherein said strips are separated from and unconnected to each of the other of said strips except by said substrate.

21. The memory of claim 18 wherein said phase change material portions have indented, exposed surfaces.

22. The memory of claim 18 wherein said phase change memory material portions are sidewall spacers.

23. The memory of claim 22 including dielectric sidewall spacers sandwiching said phase change memory material portions.

24. The memory of claim 18 wherein said strips include an ovonic threshold switch.

25. The memory of claim 18 including lower electrodes under said phase change memory material portions and wherein said phase change memory material portions are self-aligned with upper and lower electrodes.

26. A system comprising:

a processor;

a static random access memory coupled to said processor; and

a phase change memory including a substrate, and a plurality of spaced, parallel elongate strips, said strips over said substrate, said strips including a plurality of spaced, singulated phase change memory material portions extending along the length of the strips, said strips including an upper electrode, over said phase change material portion, extending along the length of the strips.

27. The system of claim 26 including a series of spaced, parallel, lower electrodes, said electrodes extending generally perpendicularly to said strips, said parallel, lower electrodes being located under said phase change memory material portions.

28. The system of claim 26 wherein said strips are separated from and unconnected to each of the other of said strips except by said substrate.

29. The system of claim 26 wherein said phase change material portions have indented, exposed surfaces.