WIRELESS PROGRAMMABLE LOGIC DEVICE

• US 20090196199A1
• Filed: 09/23/2008
• Published: 08/06/2009
• Est. Priority Date: 01/31/2007
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Markison, Timothy W., ROFOUGARAN, AHMADREZA (REZA)
• Granted Patent: US 8,254,319 B2
• Time in Patent Office: Days
• US Class Current: 370/254
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration

Abstract

A programmable logic device includes a control module, a plurality of input/output modules, and a plurality of configurable logic and millimeter wave (MMW) transceiver modules (CXM). The control module is operable to: receive a programming instruction; identify a set of the plurality of CXMs based on the programming instruction; identify at least one of the plurality of input/output modules based on the programming instruction; determine configuration of the set of the plurality of CXMs and the at least one of input/output modules in accordance with the programming instruction; and allocate wireless communication resources of the programmable logic device to support the configuration of the set of the plurality of CXMs and the at least one of the plurality of input/output modules.

Claims

1. A programmable logic device comprises:

a control module;

a plurality of input/output modules; and

a plurality of configurable logic and millimeter wave (MMW) transceiver modules (CXM), wherein the control module is operable to;

receive a programming instruction;

identify a set of the plurality of CXMs based on the programming instruction;

identify at least one of the plurality of input/output modules based on the programming instruction;

determine configuration of the set of the plurality of CXMs and the at least one of input/output modules in accordance with the programming instruction; and

allocate wireless communication resources of the programmable logic device to support the configuration of the set of the plurality of CXMs and the at least one of the plurality of input/output modules.

2. The programmable logic device of claim 1 further comprises:

a clock source circuit that includes;

an oscillation module that generates at least one oscillation; and

a MMW transmitter section coupled to transmit the at least one oscillation as at least one MMW clock source signals.

3. The programmable logic device of claim 1, wherein the control module comprises:

a control unit operable to;

identify the set of the plurality of CXMs and the at least one of the plurality of input/output modules based on the programming instruction;

determine the configuration of the set of the plurality of CXMs and the at least one of input/output modules;

generate a configuration message in accordance with the configuration;

allocate the wireless communication resources to support the configuration of the set of the plurality of CXMs and the at least one of the plurality of input/output modules;

generate a wireless communication resource allocation message in accordance with the allocation of the wireless communication resources; and

a MMW transceiver operable to;

convert the configuration message into a MMW configuration signal;

convert the wireless communication resource allocation message into a MMW resource allocation signal; and

transmit the MMW configuration signal and the MMW resource allocation signal via at least one set-up wireless communication resource.

4. The programmable logic device of claim 3 further comprises at least one of:

the control unit coupled to at least one of the plurality of input/output modules to receive the programming instruction;

the MMW transceiver coupled to;

receive a MMW program signal from the at least one of the plurality of input/output modules;

convert the MMW program signal into the programming instruction; and

convey the programming instruction to the control unit.

5. The programmable logic device of claim 3, wherein the control module further comprises:

a clock source circuit that includes;

an oscillation module that generates at least one oscillation; and

a MMW transmitter section coupled to transmit the at least one oscillation as at least one MMW clock source signals.

6. The programmable logic device of claim 1, wherein a configurable logic block and MMW transceiver module of the plurality of CXMs comprises:

one or more configurable logic blocks, wherein a configurable logic block of the one or more configurable logic blocks includes an input, an output, and a clock input; and

a MMW transceiver coupled to the one or more configurable logic blocks, wherein the MMW transceiver functions to;

receive an inbound MMW signal;

convert the inbound MMW signal into an input signal;

convey the input signal to the input of at least one of the one or more configurable logic blocks;

receive an output signal from the output of the at least one of the one or more configurable logic blocks; and

convert the output signal into an outbound MMW signal.

7. The programmable logic device of claim 6, wherein the MMW transceiver comprises:

a baseband processing module coupled to;

convert an inbound symbol stream into the input signal; and

convert the output signal into an outbound symbol stream;

a MMW front-end coupled to;

convert the inbound MMW signal into the inbound symbol stream;

convert the outbound symbol stream into the outbound MMW signal;

receive a MMW clock source signal; and

convert the MMW clock source signal into an oscillation; and

a clock recovery circuit coupled to convert the oscillation into a clock signal, wherein the clock recovery circuit conveys the clock signal to the clock input of the at least one of the one or more of the configurable logic blocks.

8. The programmable logic device of claim 7, wherein the MMW transceiver further comprises:

a switch matrix operable to couple the input or the output of a first one of the one or more configurable logic blocks to the input or the output of a second one of the one or more configurable logic blocks.

9. The programmable logic device of claim 7, the MMW front-end comprises:

a transmit section coupled to convert the inbound MMW signal into the inbound symbol stream based on a transmit local oscillation;

a receive section coupled to convert the outbound symbol stream into the outbound MMW signal based on a receive local oscillation;

a local oscillation generator coupled to generate the transmit and receive local oscillations;

a clock local oscillation generator coupled to generate a clock reference oscillation;

a clock receiver section coupled to convert the MMW clock source signal into a down converted signal based on the clock reference oscillation; and

a calibration circuit coupled to generate an adjust signal based on the down converted signal, wherein the clock local oscillation generator adjusts the clock reference oscillation based on the adjust signal to produce the oscillation.

10. The programmable logic device of claim 1, wherein an input/output module of the plurality of input/output modules comprises:

one or more input/output (I/O) blocks, wherein an I/O block of the one or more I/O blocks includes a data input, a data output, and a clock input; and

a MMW transceiver coupled to the one or more I/O blocks, wherein the MMW transceiver functions to;

receive an inbound MMW signal;

convert the inbound MMW signal into an input signal;

convey the input signal to the input of at least one of the I/O blocks;

receive an output signal from the output of the at least one of the I/O blocks; and

convert the output signal into an outbound MMW signal.

11. The programmable logic device of claim 1 further comprises at least one of:

one or more memory modules, wherein a memory module of the one or more memory modules includes one or more memory blocks and a memory MMW transceiver; and

one or more multiplier modules, wherein a multiplier module of the one or more multiplier modules includes one or more multiplier blocks and a multiplier MMW transceiver.

12. The programmable logic device of claim 1 further comprises:

a plurality of local CXMs, wherein a local CXM of the plurality of local CXMs includes a set of the plurality of CXMs;

a plurality of regions, wherein a region of the plurality of regions includes a set of the plurality of local CXMs, wherein a wireless communication resource of the wireless communication resources includes at least one of a division multiple access slot and a channel of a frequency band, wherein the wireless communication resources are partitioned into a frequency band section for clock source signals communications, a frequency band for set-up communications, a frequency band section for communications within the local CXM, a frequency band section for communications within the region, and a frequency band for communications between two or more of the plurality of regions.

13. The programmable logic device of claim 1 further comprises:

a plurality of wireless communication transmission mediums, wherein the control module allocates a wireless communication transmission medium of the plurality of wireless communication transmission mediums for a wireless communication resource of the wireless communication resources allocated to support the configuration.

14. A programmable logic device comprises:

a plurality of input/output modules; and

a plurality of configurable logic and millimeter wave (MMW) transceiver modules (CXM), wherein, in response to a programming instruction, a set of the plurality of CXMs and at least one of the plurality of input/output modules are wirelessly connected via one or more wireless communication resources.

15. The programmable logic device of claim 14 further comprises:

a clock source circuit that includes;

an oscillation module that generates at least one oscillation; and

a MMW transmitter section coupled to transmit the at least one oscillation as at least one MMW clock source signals.

16. The programmable logic device of claim 14 further comprises:

the set of the plurality of CXMs and the at least one of the plurality of input/output modules receives the programming instruction via at least one set-up wireless communication resource.

17. The programmable logic device of claim 14, wherein a configurable logic block and MMW transceiver module of the plurality of CXMs comprises:

one or more configurable logic blocks, wherein a configurable logic block of the one or more configurable logic blocks includes an input, an output, and a clock input; and

a MMW transceiver coupled to the one or more configurable logic blocks, wherein the MMW transceiver functions to;

receive an inbound MMW signal;

convert the inbound MMW signal into an input signal;

convey the input signal to the input of at least one of the one or more configurable logic blocks;

receive an output signal from the output of the at least one of the one or more configurable logic blocks; and

convert the output signal into an outbound MMW signal.

18. The programmable logic device of claim 17, wherein the MMW transceiver comprises:

a baseband processing module coupled to;

convert an inbound symbol stream into the input signal; and

convert the output signal into an outbound symbol stream;

a MMW front-end coupled to;

convert the inbound MMW signal into the inbound symbol stream;

convert the outbound symbol stream into the outbound MMW signal;

receive a MMW clock source signal; and

convert the MMW clock source signal into an oscillation; and

a clock recovery circuit coupled to convert the oscillation into a clock signal, wherein the clock recovery circuit conveys the clock signal to the clock input of the at least one of the one or more of the configurable logic blocks.

19. The programmable logic device of claim 18, wherein the MMW transceiver further comprises:

a switch matrix operable to couple the input or the output of a first one of the one or more configurable logic blocks to the input or the output of a second one of the one or more configurable logic blocks.

20. The programmable logic device of claim 18, the MMW front-end comprises:

a transmit section coupled to convert the inbound MMW signal into the inbound symbol stream based on a transmit local oscillation;

a receive section coupled to convert the outbound symbol stream into the outbound MMW signal based on a receive local oscillation;

a local oscillation generator coupled to generate the transmit and receive local oscillations;

a clock local oscillation generator coupled to generate a clock reference oscillation;

a clock receiver section coupled to convert the MMW clock source signal into a down converted signal based on the clock reference oscillation; and

a calibration circuit coupled to generate an adjust signal based on the down converted signal, wherein the clock local oscillation generator adjusts the clock reference oscillation based on the adjust signal to produce the oscillation.

21. The programmable logic device of claim 14, wherein an input/output module of the plurality of input/output modules comprises:

one or more input/output (I/O) blocks, wherein an I/O block of the one or more I/O blocks includes a data input, a data output, and a clock input; and

a MMW transceiver coupled to the one or more I/O blocks, wherein the MMW transceiver functions to;

receive an inbound MMW signal;

convert the inbound MMW signal into an input signal;

convey the input signal to the input of at least one of the I/O blocks;

receive an output signal from the output of the at least one of the I/O blocks; and

convert the output signal into an outbound MMW signal.

22. The programmable logic device of claim 14 further comprises at least one of:

one or more memory modules, wherein a memory module of the one or more memory modules includes one or more memory blocks and a memory MMW transceiver; and

one or more multiplier modules, wherein a multiplier module of the one or more multiplier modules includes one or more multiplier blocks and a multiplier MMW transceiver.

23. The programmable logic device of claim 14 further comprises:

a plurality of local CXMs, wherein a local CXM of the plurality of local CXMs includes a set of the plurality of CXMs;

a plurality of regions, wherein a region of the plurality of regions includes a set of the plurality of local CXMs, wherein a wireless communication resource of the wireless communication resources includes at least one of a division multiple access slot and a channel of a frequency band, wherein the wireless communication resources are partitioned into a frequency band section for clock source signals communications, a frequency band for set-up communications, a frequency band section for communications within the local CXM, a frequency band section for communications within the region, and a frequency band for communications between two or more of the plurality of regions.

24. The programmable logic device of claim 14 further comprises:

a plurality of wireless communication transmission mediums, wherein the programming instruction indicates allocation of a wireless communication transmission medium of the plurality of wireless communication transmission mediums for a wireless communication resource of the one or more wireless communication resources.