Systems and Methods for Testing and Diagnosing Delay Faults and For Parametric Testing in Digital Circuits

• US 20090198461A1
• Filed: 02/06/2008
• Published: 08/06/2009
• Est. Priority Date: 02/06/2008
• Status: Active Grant

• Current Assignee: DFT Microsystems, Inc.
• Original Assignee: DFT Microsystems, Inc.
• Inventors: Hafed, Mohamed M.
• Granted Patent: US 7,917,319 B2
• Time in Patent Office: Days
• US Class Current: 702/69
• CPC Class Codes: G01R 31/31858 Delay testing

Abstract

Delay-fault testing and parametric analysis systems and methods utilizing one or more variable delay time-base generators. In embodiments of the delay-fault testing systems, short-delay logic paths are provided with additional scan-chain memory elements and logic that, in conjunction with the one or more variable-delay time-base generators, provides the effect of over-clocking without the need to over-clock. Related methods provide such effective over-clocking. In embodiments of parametric analysis systems, test point sampling elements and analysis circuitry are clocked as a function of the output of the one or more variable-delay time-base generators to provide various parametric analysis functionality. Related methods address this functionality.

Claims

1. An integrated circuit, comprising:

combinational logic that includes a number N of data paths;

a functional clock network responsive to a reference clock so as to provide a functional clock signal;

a time-base generator responsive to the reference clock so as to provide a time-base clock signal;

a scan chain comprising at least N scannable memory elements each operatively connected to said functional clock network and to corresponding respective data paths of said N data paths so as to capture data from said corresponding respective data paths in response to the functional clock signal; and

an additional memory element operatively connected to said time-base generator and to a particular data path of said N data paths so as to capture data from said particular data path in response to said time-base clock signal.

2. An integrated circuit according to claim 1, wherein said additional memory element has a first output and the integrated circuit further comprises fault-capture logic in communication with said additional memory element for receiving the first output.

3. An integrated circuit according to claim 2, wherein said fault-capture logic includes:

a XOR logic gate for XORing together data output from the one of said N scannable memory elements connected to said particular data path and said first output of said additional memory element so as to provide a XORed output; and

an additional scannable memory element for capturing the XORed output of said XOR logic gate in response to said functional clock signal. (You should replace the NORs in the claims with XORs. I did not go through all of them).

4. An integrated circuit according to claim 3, wherein said additional scannable memory element is on said scan chain.

5. An integrated circuit according to claim 1, wherein said time-base generator comprises:

modulation circuitry for generating a rapidly varying phase signal as a function of said first clock signal; and

a phase filter for receiving the rapidly varying phase signal and filtering therefrom unwanted high-frequency phase components so as to output the time-base signal.

6. An integrated circuit according to claim 5, wherein said modulation circuitry includes clock-selection circuitry for continually selecting from among differing-delay versions of the reference clock signal so as to generate the rapidly varying phase signal.

7. An integrated circuit according to claim 6, wherein said clock-selection circuitry includes a multiplexer receiving differing delayed versions of the reference clock signal and a circular memory for driving selection of said differing delayed versions.

8. An integrated circuit, comprising:

combinational logic having a plurality of data paths; and

delay-fault testing circuitry that includes;

a functional clock circuit for clocking ones of said plurality of data paths with a first clock signal having a period;

a time-base clock circuit for, simultaneously with the clocking by said functional clock circuit, clocking at least one of said plurality of data paths with a second clock signal that is delayed or advanced relative to said first clock signal; and

launch-capture circuitry operatively configured to provide said at least one of said plurality of data paths with an effective launch-capture cycle that is smaller than the period of the first clock signal.

9. An integrated circuit according to claim 8, wherein said at least one of said plurality of data paths is a short delay path.

10. An integrated circuit according to claim 8, further comprising a scan chain for testing ones of said plurality of data paths of said combinational logic, wherein said launch-capture includes first and second memory elements connected to said at least one of said plurality of data paths in parallel with one another, said first memory element being clocked by the first clock signal and said second memory element being clocked by the second clock signal, said first and second memory elements being on said scan chain.

11. An integrated circuit according to claim 10, wherein said first and second and having corresponding respective outputs, said launch-capture circuitry comprising fault-capture logic that operates on the corresponding respective outputs to provide a signal that a delay fault has occurred.

12. An integrated circuit according to claim 11, wherein said delay-fault logic includes:

a XOR logic gate for XORing said corresponding respective outputs with one another so as to provide a XORed output; and

a third memory element for capturing said XORed output of said XOR logic gate in response to said first clock signal.

13. An integrated circuit according to claim 8, wherein said time-base clock circuit comprises:

modulation circuitry for generating a rapidly varying phase signal as a function of said first clock signal; and

a phase filter for receiving the rapidly varying phase signal and filtering therefrom unwanted high-frequency phase components so as to output the time-base signal.

14. An integrated circuit according to claim 13, wherein said modulation circuitry includes clock-selection circuitry for continually selecting from among differing-delay versions of the reference clock signal so as to generate the rapidly varying phase signal.

15. An integrated circuit according to claim 14, wherein said clock-selection circuitry includes a multiplexer receiving differing delayed versions of the reference clock signal and a circular memory for driving selection of said differing delayed versions.

16. A method of performing delay-fault testing on an integrated circuit, comprising:

providing an integrated circuit comprising combinational logic that includes a plurality of data paths outputting corresponding respective data bits to a plurality of memory elements;

clocking the combinational logic and ones of the plurality of memory elements with a first clock signal having a period;

simultaneously with said clocking with the first clock signal, providing a particular memory element of the plurality of memory elements with a shorter launch-capture cycle that is shorter than the period of the first clock signal, the shorter launch-capture cycle being implemented using two separate, but simultaneous, delayed clocks; and

determining whether a delay fault occurred on the particular data path of the plurality of data paths corresponding to the particular memory element provided with the shorter launch-capture cycle as a function of the shorter launch-capture cycle.

17. A method according to claim 16, wherein the plurality of data paths have differing delays and the method further comprises selecting the particular data path due to the particular data path having a short delay relative to the differing delays.

18. A method according to claim 16, wherein the combinational logic has a mission-mode speed and said clocking with said first clock signal includes clocking at the mission-mode speed.

19. A method according to claim 16, wherein said providing with a shorter launch-capture cycle includes clocking the particular memory element with a second clock signal that is delayed by a predetermined amount.

20. A method according to claim 19, further comprising generating the second clock signal by continually selecting between differing delayed versions of a reference clock to provide a combined signal and, then, phase-filtering the combined signal.

21. A method according to claim 16, wherein said determining of whether a delay fault occurred includes performing a logical operation on an output of the particular memory element and an output of an additional memory element operatively connected to the particular data path in parallel with the particular memory element.

22. A method according to claim 21, wherein said performing of the logical operation includes XORing together the output of the particular memory element and the output of an additional memory element.

23. A method according to claim 21, wherein said performing of the logical operation produces a logic result and said determining of whether a delay fault occurred includes capturing the logic result using a memory element clocked with the first clock signal.

24. A method of implementing delay-fault testing for an integrated circuit, comprising:

during a design phase of designing an integrated circuit, identifying small delay paths from a plurality of data paths;

providing ones of the plurality of data paths with a corresponding respective plurality of first scannable memory elements;

providing the integrated circuit with additional, second scannable memory elements to the outputs of the small delay paths;

providing the integrated circuit with further, third scannable memory elements in communication with corresponding respective ones of the second scannable memory elements, the third scannable memory elements for capturing delay-fault signals;

providing the integrated circuit with a functional clock network for providing a first clock signal to the plurality of data paths and the plurality of first scannable memory elements;

providing the integrated circuit with a time-base generator for providing a second clock signal to the second scannable memory elements, the second clock signal having a delay relative to the first clock signal;

programming the time-base generator so that the delay is an optimal value;

scanning appropriate data values for transition fault testing into the plurality of first scannable memory elements and the second scannable memory elements;

performing the transition fault testing using the first and second clock signals simultaneously with one another; and

subsequent to said performing of the transition fault testing, scanning test values out of at least the third scannable memory elements.

25. A method according to claim 24, further comprising programming the time-base generator with differing values and determining ones of the differing values that correctly pass known-good devices and that correctly measure small delay paths.

26. An integrated circuit, comprising:

a functional clock network for providing a first clock signal;

combinational logic responsive to the first clock signal;

a time-base generator for providing a second clock signal having a programmed delay relative to said first clock signal;

a test-point sampling element having a data input in communication with said functional clock network or said combinational logic for sampling values of a signal under test, said test-point sampling element responsive to the second clock signal; and

analysis circuitry in communication with said test-point sampling element, said analysis circuitry for counting as a function of the values sampled by said test-point sampling element.

27. An integrated circuit according to claim 26, wherein said analysis circuitry includes:

a counter; and

a first sampler operatively connected between said test-point sampling element and said counter, said first sampler for sampling the values sampled by said test-point sampling element as a function of the second clock signal.

28. An integrated circuit according to claim 27, wherein said analysis circuitry further includes:

a divider for dividing the second clock signal into a sampling clock signal and a complementary sampling clock signal; and

a second sampler operatively connected between said test-point sampling element and said counter, said first sampler for sampling the values sampled by said test-point sampling element as a function of the complementary sampling clock signal;

wherein said first sampler is responsive to said sampling clock signal.

29. An integrated circuit according to claim 28, wherein the second clock signal has a period and said divider is a full-cycle programmable divider for dividing the period of the second clock signal by integer values.

30. An integrated circuit according to claim 28, further including:

an AND logic gate for ANDing together outputs of said first and second samplers, and

a multiplexer coupled between said first sampler and said counter and between said AND logic gate and said counter, said multiplexer for selectively providing one or the other of the outputs of said first and second samplers to said counter.

31. A method of measuring a parameter of a signal under test in an integrated circuit, comprising:

providing an integrated circuit that generates a periodic signal having a frequency;

generating from within the integrated circuit a time-base signal having the frequency of the periodic signal and a variable delay relative to the periodic signal;

sampling, with a one-bit sampler over a number N of cycles of the time-base signal, the periodic signal in response to the time-base signal a plurality of times each having a differing value of the variable delay; and

for each of the plurality of times, counting over the N cycles the number of sampled occurrences of a particular bit value captured by the one-bit sampler.

32. A method according to claim 31, wherein said generating of the time-base signal comprises continually selecting between differing delayed versions of a reference clock to provide a combined signal and, then, phase-filtering the combined signal.

33. A method according to claim 32, wherein said generating of the time-base signal further comprises generating a phase-delay selection signal for continually selecting between the differing delayed versions of the reference clock as a function of contents of a circulating memory.

34. A method according to claim 33, further comprising changing the contents of the circular memory so as to provide the differing value of the variable delay for ones of the plurality of times of said sampling.

35. A method according to claim 31, wherein the parameter of the signal under test is delay and the method comprises:

setting a current delay value in time-base signal;

using the current delay, counting the number of times the one-bit sampler generate either a logical “

1”

or a logical “

0”

over the N cycles so as to provide a count value;

if the count value after N cycles is within a desired tolerance of N/2, reporting the current delay as a measured delay value;

if the count value after N cycles is either greater than or less than, depending on whether the logical “

1”

or logical “

0”

is being counted, N/2, incrementing or decrementing the current delay value; and

following said incrementing or decrementing, repeating said counting, said reporting and said incrementing or decrementing until the measured delay value is reported.

36. A method according to claim 35, wherein said sampling of the periodic signal includes sampling a mission-mode clock signal.

37. A method according to claim 35, wherein it is desired to measure temperature effects on the delay, the method further comprising:

providing a temperature-sensitive delay element in communication with a input of the one-bit sampler, the temperature-sensitive delay element providing the periodic signal;

performing said counting, said reporting and said incrementing or decrementing in logical order over a period of time so as to produce a plurality of measured delay values.

38. A method according to claim 37, wherein said providing of the temperature-sensitive delay element includes providing the temperature-sensitive delay element proximate a logic block and the method further comprises, while performing said counting, said reporting and said incrementing or decrementing in logical order over the period of time, increasing switching activity in the logic block so as to increase the temperature of the temperature-sensitive delay element.

39. A method according to claim 31, wherein the parameter of the signal under test is jitter and the method comprises:

sweeping the variable delay of the time base signal; and

while sweeping the variable delay, performing said sampling and said counting so as to generate a set of counts.

40. A method according to claim 39, further comprising:

repeatingly sweeping the variable delay;

repeatingly counting so as to generate a series of sets of counts; and

using the series of sets of counts, constructing a jitter histogram and/or a probability distribution function.

41. A method of measuring power supply noise in an integrated circuit, comprising:

providing an integrated circuit that includes a delay element that generates a periodic signal in response to a power supply signal, the periodic signal having a frequency;

determining a mean edge location of the periodic signal;

generating from within the integrated circuit a time-base signal having the frequency of the periodic signal and a variable delay relative to the periodic signal;

setting the variable delay to a delay value corresponding to the mean edge location of the periodic signal;

sampling, with a one-bit sampler, the periodic signal in response to the time base signal over a period of time using the delay value set above;

generating a sampling clock signal and a complementary sampling clock signal as a function of the time-base signal;

while sampling with the one-bit sampler, sampling, using a first analysis sampler, an output of the one-bit sampler in response to the sampling clock signal;

while sampling with the one-bit sampler, sampling, using a second analysis sampler, the output of the one-bit sampler in response to the complementary sampling clock signal;

while sampling with the one-bit sampler, ANDing together outputs of the first and second analysis samplers so as to provide ANDing results;

accumulating the ANDing results over a number M of cycles of the time-base signal.

42. A method according to claim 41, further comprising performing said accumulating a number N of times, wherein for each of the N times the sampling clock signal and complementary clock signal are differing divisions of the time-base signal.

43. A method according to claim 42, further comprising generating an N-long count vector of the ANDing results.

44. A method according to claim 43, further comprising performing a fast-Fourier transform analysis on the N-long count vector.

45. A method according to claim 43, further comprising analyzing the N-long count vector to identify power supply noise.