Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device
First Claim
1. A system comprising:
- an integrated circuit buffer device including;
a first interface to receive control information;
a second interface to output the control information and receive data; and
a register to store a value that indicates a number of integrated circuit memory devices to perform a memory access in response to the control information, wherein each memory device included in the number of integrated circuit memory devices, indicated by the value, provides a portion of the data from a corresponding memory access;
a first integrated circuit memory device to output a first portion of the data;
a first signal path coupled to the integrated circuit buffer device and the first integrated circuit memory device, the first signal path to convey the first portion of the data from the first integrated circuit memory device to the integrated circuit buffer device;
a second integrated circuit memory device to output a second portion of the data;
a second signal path coupled to the integrated circuit buffer device and the second integrated circuit memory device, the second signal path to convey the second portion of data from the second integrated circuit memory device to the integrated circuit buffer device; and
a third signal path coupled to the integrated circuit buffer device and the first and second integrated circuit memory devices, the third signal path to convey the control information from the integrated circuit buffer device to both the first and second integrated circuit memory devices.
1 Assignment
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Accused Products
Abstract
Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.
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Citations
25 Claims
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1. A system comprising:
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an integrated circuit buffer device including; a first interface to receive control information; a second interface to output the control information and receive data; and a register to store a value that indicates a number of integrated circuit memory devices to perform a memory access in response to the control information, wherein each memory device included in the number of integrated circuit memory devices, indicated by the value, provides a portion of the data from a corresponding memory access; a first integrated circuit memory device to output a first portion of the data; a first signal path coupled to the integrated circuit buffer device and the first integrated circuit memory device, the first signal path to convey the first portion of the data from the first integrated circuit memory device to the integrated circuit buffer device; a second integrated circuit memory device to output a second portion of the data; a second signal path coupled to the integrated circuit buffer device and the second integrated circuit memory device, the second signal path to convey the second portion of data from the second integrated circuit memory device to the integrated circuit buffer device; and a third signal path coupled to the integrated circuit buffer device and the first and second integrated circuit memory devices, the third signal path to convey the control information from the integrated circuit buffer device to both the first and second integrated circuit memory devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A system comprising:
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a first integrated circuit memory device and a second integrated circuit memory device; an integrated circuit buffer device including; a first interface to receive control information; a second interface to output the control information and receive first data; and registers to store information indicating a number of signal paths, a number of signal lines included in each signal path of the number of signal paths coupled between the integrated circuit buffer device and each of the first and second integrated circuit memory devices; a first signal path coupled to the integrated circuit buffer device and the first integrated circuit memory device, the first signal path to convey a first portion of the first data from the first integrated circuit memory device to the integrated circuit buffer device; a second signal path coupled to the integrated circuit buffer device and the second integrated circuit memory device, the second signal path to convey a second portion first data from the second integrated circuit memory device to the integrated circuit buffer device; and a third signal path coupled to the integrated circuit buffer device and the first and second integrated circuit memory devices, the third signal path to convey the control information from the integrated circuit buffer device to both the first and second integrated circuit memory devices. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. An integrated circuit buffer device including:
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a first interface to receive control information; a second interface to output the control information and transfer first data associated with the control information; and a register to store a value that indicates a number of integrated circuit memory devices to perform a memory access in response to the control information, wherein each memory device included in the number of integrated circuit memory devices, indicated by the value, transfers a portion of the data from a corresponding memory access. - View Dependent Claims (20, 21, 22, 23, 24)
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25. A module comprising:
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a first integrated circuit memory device and a second integrated circuit memory device; an integrated circuit buffer device coupled to the first integrated circuit memory device and the second integrated circuit memory device, the integrated circuit buffer device including; a first interface to receive control information; a second interface to output the control information and receive first data; and registers to store information indicating a number of signal paths, a number of signal lines included in each signal path of the number of signal paths coupled between the integrated circuit buffer device and each of the first and second integrated circuit memory devices.
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Specification