MECHANISMS FOR COMMUNICATING WITH AN ASYNCHRONOUS MEMORY MOVER TO PERFORM AMM OPERATIONS

• US 20090198937A1
• Filed: 02/01/2008
• Published: 08/06/2009
• Est. Priority Date: 02/01/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Blackmore, Robert S., Xue, Hanhong, Arimilli, Ravi K., Kim, Chulho, Sinharoy, Balaram
• Granted Patent: US 8,245,004 B2
• Time in Patent Office: Days
• US Class Current: 711/165
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE

Abstract

A data processing system includes a set of architected registers within which the processor places state and other information to communicate with the asynchronous memory mover in order to initiate and control an AMM operation. The asynchronous memory mover performs an asynchronous memory move (AMM) operation in response to receiving a set of parameters within the architected registers, which parameters are associated with an AMM store instruction executed by the processor to initiates a move of data in virtual space before placing the information in the architected registers. The architected registers are processor architected registers, defined on a per thread basis by a compiler, or memory mapped architected registers allocated for communicating with the asynchronous memory mover during a bind and subsequent execution of an application. The architected registers are also utilized to store state information to enable a restore to a point before execution of the AMM operation.

Claims

1. A data processing system comprising:

a processor;

a memory coupled to the processor and including a plurality of physical locations having real addresses for storing data;

an asynchronous memory mover coupled to the processor and which, in response to receiving a set of parameters associated with a data move operation initiated by the processor utilizing a source effective address and a destination effective address, performs an asynchronous memory move (AMM) operation by which the actual data is moved from a first memory location having a source real address corresponding to the source effective address to a second memory location having a destination real address corresponding to the destination effective address; and

a plurality of registers within which the processor places state and other information to communicate said information to the asynchronous memory mover in order to initiate and control the AMM operation.

2. The data processing system of claim 1, wherein the registers are processor architected registers, which are defined on a per thread basis by a compiler of an application being executed by the processor.

3. The data processing system of claim 1, wherein the registers are memory mapped architected registers that are allocated for communicating with the asynchronous memory mover during a bind and subsequent execution of an application.

4. The data processing system of claim 1, wherein, responsive to a condition that causes a pause or stop of the AMM operation, said asynchronous memory mover further comprises:

logic for saving a current state information of the AMM operation within the registers; and

logic for retrieving the state information from the processor architected registers when the asynchronous memory mover initiates a resumption of the AMM operation.

5. The data processing system of claim 1, wherein responsive to receipt by the processor of an AMM terminate ST instruction, the processor responds by triggering the asynchronous memory mover to stop the corresponding ongoing AMM operation and restore the registers to an original state.

6. In a data processing system having a processor, a memory, an asynchronous memory mover (AMM mover) coupled to the processor, and a plurality of architected registers, a method comprising:

identifying a plurality of the architected registers as memory mover status and parameter holding registers for utilization to communicate information between the processor and the asynchronous memory mover;

in response to receiving an asynchronous data move (AMM) Store (ST) instruction having a set of parameters for performing an AMM operation;

initiating an data move in virtual address space utilizing relevant parameters from the set of parameters;

forwarding the set of parameters to specific ones of the memory mover status and parameter holding registers;

wherein the asynchronous memory mover responds to a detected presence within the specific memory mover status and parameter holding registers of the set of parameters by launching an AMM operation generated by a subset of the set of parameters.

7. The method of claim 6, further comprising:

placing current state information within one or more of the memory mover status registers prior to launching the AMM operation; and

responsive to a detected failure of the AMM operation to complete, retrieving the state information from the one or more memory mover status registers to restart operations at a point prior to the launch of the AMM operation.

8. The method of claim 6, wherein the registers are processor architected registers, which are defined on a per thread basis by a compiler of an application being executed by the processor.

9. The method of claim 6, wherein the registers are memory mapped architected registers that are allocated for communicating with the asynchronous memory mover during a bind and subsequent execution of an application.

10. The method of claim 6, wherein, responsive to a condition that causes one of a pause and a stop of the AMM operation, said method further comprises:

saving a current state information of the AMM operation within the registers; and

retrieving the state information from the processor architected registers when the asynchronous memory mover initiates a resumption of the AMM operation.

11. The method of claim 10, wherein responsive to receipt by the processor of an AMM terminate ST instruction, the method further comprises triggering the asynchronous memory mover to stop the corresponding ongoing AMM operation and restore the registers to an original state.