ASYNCHRONOUS MEMORY MOVE ACROSS PHYSICAL NODES (DUAL-SIDED COMMUNICATION FOR MEMORY MOVE)

• US 20090198955A1
• Filed: 02/01/2008
• Published: 08/06/2009
• Est. Priority Date: 02/01/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Blackmore, Robert S., Xue, Hanhong, Arimilli, Ravi K., Kim, Chulho, Sinharoy, Balaram
• Granted Patent: US 8,275,963 B2
• Time in Patent Office: Days
• US Class Current: 711/213
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Abstract

A distributed data processing system includes: (1) a first node with a processor, a first memory, and asynchronous memory mover logic; and connection mechanism that connects (2) a second node having a second memory. The processor includes processing logic for completing a cross-node asynchronous memory move (AMM) operation, wherein the processor performs a move of data in virtual address space from a first effective address to a second effective address, and the asynchronous memory mover logic completes a physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address. The data is transmitted via the connection mechanism connecting the two nodes independent of the processor.

Claims

1. A distributed data processing system comprising:

a first node having;

a processor;

a memory subsystem including at least a first memory coupled to the processor and including a plurality of physical locations having real addresses for storing data; and

asynchronous memory mover logic;

a second node having a second memory with at least one physical location with a real address for storing data;

a connection mechanism for coupling said first node to said second node; and

processing logic for completing a cross-node asynchronous memory move (AMM) operation, wherein the processor performs a move of data in virtual address space from a first effective address to a second effective address, and the asynchronous memory mover logic completes a physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address, wherein the data is transmitted via the connection mechanism connecting the two nodes independent of the processor.

2. The distributed data processing system of claim 1, wherein the second node and the first node share an effective address space, with at least a first set of effective addresses mapped to physical memory in the first memory and a second set of effective addresses mapped to physical locations in the second memory.

3. The distributed data processing system of claim 1, wherein the first node further comprises:

an instruction fetch unit that retrieves instruction from an instruction stream, where the instructions are provided by an instruction set architecture (ISA) supported by the processor, and where the ISA includes an AMM store instruction that comprises a source effective address, a destination effective address, a count value for the amount of data to be moved, and an entry indicating a destination node identifier (ID) from among the first node and the second node; and

processing logic for;

evaluating a second node to which the AMM ST instruction initiates a move of data; and

providing the destination node ID of the second node to the AMM mover when the AMM operation moves data from memory in the first node to memory in the second node.

4. The distributed data processing system of claim 1, wherein the first node and second node are within a same symmetric multiprocessor (SMP) system.

5. The distributed data processing system of claim 1, wherein the first node and the second node are located across different symmetric multiprocessors (SMPs).

6. The distributed data processing system of claim 5, wherein the connection mechanism includes a network fabric.

7. In a distributed data processing system having:

(1) a first node with a processor, a memory; and

asynchronous memory mover logic;

connected via an interconnect to (2) a second node having a second memory, a method comprising;

performing a cross-node asynchronous memory move (AMM) operation, wherein the processor performs a move of data in virtual address space from a first effective address to a second effective address and the asynchronous memory mover logic completes a physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address, wherein the data is transmitted via an interconnect connecting the two nodes independent of the processor.

8. The method of claim 7, wherein the second node and the first node share an effective address space, with at least a first set of effective addresses mapped to physical memory in the first memory and a second set of effective addresses mapped to physical locations in the second memory.

9. The method of claim 7, further comprising:

receiving the AMM ST instruction from an instruction stream generated during program compilation, wherein the AMM ST instruction is an instruction within the instruction set architecture that is supported by the processor and includes a source effective address, a destination effective address, a count value for the amount of data to be moved, and an entry indicating a destination node identifier (ID) from among the first node and the second node;

determining a destination node ID of the second node when the AMM operation moves data from memory in the first node to memory in the second node; and

providing the destination node ID of the second node to the AMM mover when the AMM operation moves data from memory in the first node to memory in the second node.

10. The method of claim 7, wherein the first node and second node are within a same symmetric multiprocessor (SMP) system.

11. The method of claim 7, wherein the first node and the second node are located across different symmetric multiprocessors (SMPs).

12. The method of claim 11, wherein the connection mechanism includes a network fabric.