System and Method for Data Processing Using a Low-Cost Two-Tier Full-Graph Interconnect Architecture

• US 20090198956A1
• Filed: 02/01/2008
• Published: 08/06/2009
• Est. Priority Date: 02/01/2008
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Arimilli, Ravi K., Rajamony, Ramakrishnan, Arimilli, Lakshminarayana B., Seminaro, Edward J., Speight, William E.
• Application Number:
  US12/024,662
• Publication Number:
  US 20090198956A1
• Time in Patent Office: Days
• US Class Current: 712/13
• CPC Class Codes: H04L 45/06 Deflection routing, e.g. hot-potato routing
• CPC Class Codes: H04L 45/12 Shortest path evaluation
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric

Abstract

A system and method are provided for implementing a two-tier full-graph interconnect architecture. In order to implement a two-tier full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the two-tier full-graph interconnect architecture. Data is then transmitted from one processor to another within the two-tier full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor chip identifier associated with a target processor to which the data is to be transmitted.

Claims

1. A data processing system, comprising:

a plurality of processors coupled to one another to create a plurality of supernodes; and

the plurality of supernodes coupled together, wherein data is transmitted from one processor to another based on an addressing scheme specifying at least a supernode identifier and a processor chip identifier associated with a target processor to which the data is to be transmitted.

2. The system of claim 1, wherein a subset of processors of the plurality of processors is associated with each supernode of the plurality of supernodes, and wherein each processor within the supernode is directly coupled to each other processor within the supernode.

3. The system of claim 1, wherein each supernode within a subset of the plurality of supernodes is directly coupled to each other supernode within the subset of the plurality of supernodes.

4. The system of claim 2, wherein the subset of processors comprises at least eight processors.

5. The system of claim 3, wherein the subset of the plurality of supernodes comprises at least five hundred and twelve supernodes.

6. The system of claim 1, wherein:

a subset of processors of the plurality of processors is associated with each supernode of the plurality of supernodes, and wherein each processor within the supernode is directly coupled to each other processor within the supernode; and

each supernode within a subset of the plurality of supernodes is directly coupled to each other supernode within the subset of supernodes.

7. The system of claim 6, wherein:

the subset of processors are coupled to each other by a set of first buses;

the subset of supernodes are coupled to each other by a set of second buses; and

data is routed from one processor in a first supernode to another processor in a second supernode using at least one routing table data structure that specifies at least one first bus and at least one second bus over which the data is to be transmitted.

8. The system of claim 7, wherein at least one of the set of first buses and the set of second buses are cache coherent buses.

9. The system of claim 7, wherein at least one of the set of first buses and the set of second buses are non-cache coherent buses.

10. The system of claim 7, wherein the set of first buses are cache coherent and wherein the set of second buses are non-cache coherent buses.

11. The system of claim 1, wherein each processor in the plurality of processors of a supernode comprises at least four communication links for coupling the processor to at least four other supernodes in the plurality of supernodes.

12. The system of claim 1, wherein each supernode of the plurality of supernodes comprises at least five hundred and eleven communication links for coupling the supernode to at least five hundred and eleven other supernodes in the plurality of supernodes.

13. The system of claim 1, wherein each processor of the plurality of processors has an integrated switch, and wherein the integrated switch in the processor implements the addressing scheme to route data from that processor to at least one other processor in the plurality of processors.

14. The system of claim 13, wherein the integrated switch in each processor of the plurality of processors utilizes one or more routing table data structures that specify pathways from the processor to other processors in the data processing system based on the supernode identifier and the processor chip identifier.

15. The system of claim 1, wherein each processor in the supernode is directly coupled to four other processors within different supernodes, the four other processors each being in separate other supernodes.

16. The system of claim 1, wherein each processor has a plurality of cores.

17. The system of claim 16, wherein the plurality of cores are homogeneous.

18. The system of claim 16, wherein the plurality of cores are heterogeneous.

19. The system of claim 1, wherein the data processing system utilizes a low-cost two-tier full-graph interconnect architecture.

20. A method, in a data processing system, comprising:

coupling a plurality of processors to one another to create a plurality of supernodes; and

coupling the plurality of supernodes together, wherein data is transmitted from one processor to another processor based on an addressing scheme specifying at least a supernode identifier and a processor chip identifier associated with a target processor to which the data is to be transmitted.