DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING BRANCH TARGET ADDRESS CACHE INCLUDING ADDRESS TYPE TAG BIT
First Claim
1. A processor, comprising:
- at least one execution unit that executes instructions; and
instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit, said instruction sequencing logic including a branch logic that outputs predicted branch target addresses for use as instruction fetch addresses, said branch logic including a branch target address prediction circuitry concurrently holding;
a first entry providing storage for a first branch target address prediction associating a first instruction fetch address with a first branch target address to be used as an instruction fetch address, wherein said first entry indicates a first instruction address type for the first instruction fetch address; and
a second entry providing storage for a second branch target address prediction associating the first instruction fetch address with a different second branch target address, wherein the second entry indicates a second instruction address type for the first instruction fetch address.
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Accused Products
Abstract
In at least one embodiment, a processor includes an execution unit and instruction sequencing logic that fetches instructions from a memory system for execution by the execution unit. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a branch target address prediction circuitry concurrently holding a first entry providing storage for a first branch target address prediction associating a first instruction fetch address with a first branch target address to be used as an instruction fetch address and a second entry providing storage for a second branch target address prediction associating the first instruction fetch address with a different second branch target address. The first entry indicates a first instruction address type for the first instruction fetch address, and the second entry indicates a second instruction address type for the first instruction fetch address.
58 Citations
12 Claims
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1. A processor, comprising:
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at least one execution unit that executes instructions; and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit, said instruction sequencing logic including a branch logic that outputs predicted branch target addresses for use as instruction fetch addresses, said branch logic including a branch target address prediction circuitry concurrently holding; a first entry providing storage for a first branch target address prediction associating a first instruction fetch address with a first branch target address to be used as an instruction fetch address, wherein said first entry indicates a first instruction address type for the first instruction fetch address; and a second entry providing storage for a second branch target address prediction associating the first instruction fetch address with a different second branch target address, wherein the second entry indicates a second instruction address type for the first instruction fetch address. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of data processing in a processor including at least one execution unit and an instruction sequencing logic containing branch logic, the branch logic including branch target address prediction circuitry, said method comprising:
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in the branch target address prediction circuitry, concurrently holding; a first entry providing storage for a first branch target address prediction associating a first instruction fetch address with a first branch target address to be used as an instruction fetch address, wherein said first entry indicates a first instruction address type for the first instruction fetch address; and a second entry providing storage for a second branch target address prediction associating the first instruction fetch address with a different second branch target address, wherein the second entry indicates a second instruction address type for the first instruction fetch address fetching instructions from a memory system for execution by at least one execution unit of the processor; the branch logic accessing the branch target address prediction circuitry with at least a tag portion of a first instruction fetch address and an instruction address type signal; and in response to said accessing, outputting the first branch target address if the instruction address type signal indicates the first instruction address type and outputting the second branch target address if the instruction address type signal indicates the second instruction address type. - View Dependent Claims (9, 10, 11, 12)
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Specification