METHOD AND SYSTEM FOR SOURCING DIFFERING AMOUNTS OF PREFETCH DATA IN RESPONSE TO DATA PREFETCH REQUESTS

• US 20090198965A1
• Filed: 02/01/2008
• Published: 08/06/2009
• Est. Priority Date: 02/01/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: ARIMILLI, RAVI K., Zhang, Lixin, Sinharoy, Balaram, Cascaval, Gheorghe C., Speight, William E.
• Granted Patent: US 8,250,307 B2
• Time in Patent Office: Days
• US Class Current: 712/207
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3455 using stride
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862

Abstract

According to a method of data processing, a memory controller receives a prefetch load request from a processor core of a data processing system. The prefetch load request specifies a requested line of data. In response to receipt of the prefetch load request, the memory controller determines by reference to a stream of demand requests how much data is to be supplied to the processor core in response to the prefetch load request. In response to the memory controller determining to provide less than all of the requested line of data, the memory controller provides less than all of the requested line of data to the processor core.

Claims

1. A method of data processing in a data processing system having a system memory controlled by a memory controller, said method comprising:

the memory controller receiving a prefetch load request from a processor core of the data processing system, wherein the prefetch load request specifies a requested line of data;

in response to receipt of the prefetch load request, the memory controller determining by reference to a stream of demand requests how much data is to be supplied to the processor core in response to the prefetch load request; and

in response to the memory controller determining to provide less than all of the requested line of data, providing less than all of the requested line of data to the processor core.

2. The method of claim 1, wherein said providing comprises the memory controller discarding the prefetch load request without providing any of the requested line of data to the processor core.

3. The method of claim 1, wherein said providing comprises providing a partial line of data to the processor core.

4. The method of claim 1, wherein said determining comprises determining a bank of the system memory accessed by at least one demand request received by the memory controller.

5. The method of claim 1, wherein said receiving comprises receiving a prefetch load request that requests less than all of the requested line of data.

6. The method of claim 1, and further comprising:

in response to the memory controller determining to provide all of the requested line of data, providing all of the requested line of data to the processor core.

7. A memory controller for a data processing system having a system memory controlled by the memory controller, wherein in response to receiving a prefetch load request from a processor core of the data processing system, said prefetch load request specifying a requested line of data, the memory controller determines by reference to a stream of demand requests how much data is to be supplied to the processor core in response to the prefetch load request and, in response to determining to provide less than all of the requested line of data, provides less than all of the requested line of data to the processor core.

8. The memory controller of claim 7, wherein in response to the determination, the memory controller discards the prefetch load request without providing any of the requested line of data to the processor core.

9. The memory controller of claim 7, wherein said memory controller provides a partial line of data to the processor core.

10. The memory controller of claim 7, wherein said memory controller determines how much data is to be supplied based upon a bank of the system memory accessed by at least one demand request received by the memory controller.

11. The memory controller of claim 7, wherein the prefetch load request requests less than all of the requested line of data.

12. The memory controller of claim 7, wherein the memory controller, responsive to determining to provide all of the requested line of data, provides all of the requested line of data to the processor core in response to the prefetch load request.

13. A data processing system, comprising:

a processor core that generates a prefetch load request;

a system memory; and

a memory controller coupled to the system memory and to the processor core, wherein in response to receiving the prefetch load request from the processor core, said prefetch load request specifying a requested line of data, the memory controller determines by reference to a stream of demand requests how much data is to be supplied to the processor core in response to the prefetch load request and, in response to determining to provide less than all of the requested line of data, provides less than all of the requested line of data to the processor core.

14. The data processing system of claim 13, wherein in response to the determination, the memory controller discards the prefetch load request without providing any of the requested line of data to the processor core.

15. The data processing system of claim 13, wherein said memory controller provides a partial line of data to the processor core.

16. The data processing system of claim 13, wherein said memory controller determines how much data is to be supplied based upon a bank of the system memory accessed by at least one demand request received by the memory controller.

17. The data processing system of claim 13, wherein the prefetch load request requests less than all of the requested line of data.

18. The data processing system of claim 13, wherein the memory controller, responsive to determining to provide all of the requested line of data, provides all of the requested line of data to the processor core in response to the prefetch load request.