METHOD AND STRUCTURE FOR ASYNCHRONOUS SKIP-AHEAD IN SYNCHRONOUS PIPELINES

• US 20090198970A1
• Filed: 01/31/2008
• Published: 08/06/2009
• Est. Priority Date: 01/31/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Jacobson, Hans, Reohr, William Robert, Emma, Philip George, Hartstein, Allan Mark
• Granted Patent: US 7,945,765 B2
• Time in Patent Office: Days
• US Class Current: 712/220
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: G06F 9/3873 Variable length pipelines, e.g. elastic pipeline

Abstract

An electronic apparatus includes a plurality of stages serially interconnected as a pipeline to perform sequential processings on input operands. A shortening circuit associated with at least one stage of the pipeline recognizes when one or more of input operands for the stage has been predetermined as appropriate for shortening and execute the shortening when appropriate.

Claims

1. An electronic apparatus, comprising:

a plurality of stages serially interconnected as a pipeline to perform sequential processings on input operands; and

a shortening circuit associated with at least one stage of said pipeline to recognize one or more of input operands for said stage for which shortening has been predetermined as appropriate and to execute said shortening when appropriate.

2. The electronic apparatus of claim 1, wherein said shortening occurs asynchronously from a system clock controlling said plurality of stages.

3. The electronic apparatus of claim 1, wherein said input operand is precluded from shortening if a processing in a stage immediately following said stage would be disrupted by said passing to said following stage.

4. The electronic apparatus of claim 1, wherein said shortening comprises one of:

passing said input operand directly to a stage immediately following said stage; and

conjoining a processing of said input operand by said stage with a processing in said stage immediately following said stage.

5. The electronic apparatus of claim 1, wherein said shortening circuit comprises at least one of:

a special case logic circuit integrated into said stage;

firmware instructions integrated into a controller controlling said electronic apparatus;

interaction with data tags;

interaction with a compiler-generated skip vector; and

stages of a finite state machine.

6. The electronic apparatus of claim 1, wherein each said plurality of serially interconnected stages comprises an output staging latch, said shortening comprising:

making the output staging latch of said stage temporarily transparent.

7. The electronic apparatus of claim 6, wherein said making said output staging latch temporarily transparent comprises asynchronously opening very briefly said output staging latch.

8. The electronic apparatus of claim 7, wherein said shortening comprises one of:

controlling a bypass switch so that said input operand passes directly to a following stage without a processing by said stage; and

conjoining a processing of said input operand by processing in both said stage and in said following stage.

9. The electronic apparatus of claim 3, wherein said input operand comprises a valid bit and said shortening is precluded by monitoring the valid bit of the input operand of said following stage.

10. The electronic apparatus of claim 1, wherein said shortening is recognized as appropriate by at least one of:

comparing bits of said input operand with bits of input operands predetermined as subject to shortening;

including a tag in said input operand containing information for shortening;

a compiler that provides instructions to be executed by said electronic apparatus;

a compiler-generated skip vector issued along with an instruction; and

stages of a finite state machine.

11. A method of shortening a pipeline processing, said method comprising:

receiving an input operand;

recognizing whether said input operand comprises an input operand predetermined to be subject to shortening; and

executing said shortening when appropriate.

12. The method of pipeline processing shortening of claim 11, wherein said shortening comprises one of:

bypassing said input operand directly to a following stage; and

conjoining a processing of said input operand by two stages such that a processing in a current stage is followed by a processing in said following stage as executed in a same clock cycle.

13. The method of pipeline processing shortening of claim 11, wherein said shortening is precluded if it would be disruptive to a processing in a following stage.

14. The method of pipeline processing shortening of claim 11, wherein said shortening comprises making temporarily transparent an output latch of a current stage receiving said input operand, in a manner asychronously from a system clock controlling said pipeline processing.

15. The method of pipeline processing shortening of claim 11, as implemented by one of:

a special case logic circuit integrated into at least one stage of said pipeline;

firmware instructions integrated into a controller controlling said pipeline;

a compiler providing instructions to be executed by said pipeline;

data tags;

a compiler-generated skip-vector; and

stages of a finite state machine.

16. A pipeline processing shortening circuit associated with a stage of a pipeline comprising a plurality of stages serially interconnected to perform sequential processings on input operands, said shortening circuit comprising:

a receiver for receiving an input operand for said stage;

a comparator for recognizing whether said input operand comprises an input operand predetermined to be subject to shortening; and

a controller for executing said shortening when recognized as appropriate.

17. The pipeline processing shortening circuit of claim 16, wherein said controller executes said shortening by asynchronously opening an output latch of said stage of said pipeline and wherein said shortening comprises one of:

said controller switching said input operand to pass directly to a following stage; and

said input operand is thereby conjoined to said following stage such that said input operand is processed by both said stage and said following stage in a same clock cycle.

18. The pipeline processing shortening circuit of claim 16, wherein said shortening is precluded if it would be disruptive to a processing in a following stage.

19. The pipeline processing shortening circuit of claim 16, wherein said controller temporarily makes transparent an output latch of a current stage receiving said input operand, in a manner asychronously from a system clock controlling said pipeline processing.

20. The pipeline processing shortening circuit of claim 16, as implemented by one of:

a special case logic circuit integrated into at least one stage of said pipeline;

firmware instructions integrated into a controller controlling said pipeline;

a compiler providing instructions to be executed by said pipeline;

data tags;

a compiler-generated skip-vector; and

stages of a finite state machine.