PARAMETER ESTIMATION BASED ON ERROR CORRECTION CODE PARITY CHECK EQUATIONS

• US 20090199074A1
• Filed: 02/03/2009
• Published: 08/06/2009
• Est. Priority Date: 02/05/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Sommer, Naftali
• Granted Patent: US 8,156,398 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/15 Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes H03M13/17 takes precedence
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
• CPC Class Codes: H03M 13/3723 using means or methods for the initialisation of the decoder
• CPC Class Codes: H03M 13/3738 with judging correct decoding
• CPC Class Codes: H03M 13/3746 with iterative decoding
• CPC Class Codes: H03M 13/6325 Error control coding in combination with demodulation

Abstract

A method for operating a memory, which includes analog memory cells, includes encoding data with an Error Correction Code (ECC) that is representable by a plurality of equations. The encoded data is stored in a group of the analog memory cells by writing respective input storage values to the memory cells in the group. Multiple sets of output storage values are read from the memory cells in the group using one or more different, respective read parameters for each set. Numbers of the equations, which are satisfied by the respective sets of the output storage values, are determined. A preferred setting of the read parameters is identified responsively to the respective numbers of the satisfied equations. The memory is operated on using the preferred setting of the read parameters.

Claims

1. A method for operating a memory that includes analog memory cells, the method comprising:

encoding data with an Error Correction Code (ECC), which is representable by a plurality of equations;

storing the encoded data in a group of the analog memory cells by writing respective input storage values to the memory cells in the group;

reading from the memory cells in the group multiple sets of output storage values using one or more different, respective read parameters for each set;

determining respective numbers of the equations that are satisfied by the sets of the output storage values;

identifying a preferred setting of the read parameters responsively to the respective numbers of the satisfied equations; and

operating on the memory using the preferred setting of the read parameters.

2. The method according to claim 1, wherein the read parameters comprise read thresholds, and wherein operating on the memory cells comprises reading the memory cells using the preferred setting of the read thresholds.

3. The method according to claim 1, wherein the read parameters comprise cross-coupling coefficients, and wherein operating on the memory comprises canceling cross-coupling interference in the output storage values using the preferred setting of the cross-coupling coefficients.

4. The method according to claim 1, wherein the ECC comprises a binary ECC, and wherein the equations comprise Boolean equations.

5. The method according to claim 1, wherein the ECC comprises a linear ECC, and wherein the equations comprise parity check equations.

6. The method according to claim 1, wherein identifying the preferred setting comprises selecting the one or more read parameters that correspond to a set of the output storage values that satisfies a maximum number of the equations.

7. The method according to claim 1, wherein operating on the memory comprises processing a set of the output storage values read using the preferred setting of the read parameters so as to decode the ECC.

8. The method according to claim 1, wherein a number of the satisfied equations at the preferred setting of the read parameters is less than a total number of the equations in the plurality.

9. The method according to claim 1, wherein identifying the preferred setting comprises selecting the setting of the read parameters at which all of the equations in the plurality are satisfied.

10. The method according to claim 1, wherein reading the sets of the output storage values comprises attempting to decode the ECC responsively to each of the sets of the output storage values.

11. The method according to claim 10, wherein identifying the preferred setting comprises selecting the setting of the read parameters at which the ECC is decoded successfully.

12. The method according to claim 10, wherein attempting to decode the ECC comprises modifying the sets of the output storage values to produce respective modified sets of the output storage values, and wherein identifying the preferred setting comprises selecting the preferred setting responsively to respective modified numbers of the equations that are satisfied by the modified sets of the output storage values.

13. The method according to claim 10, wherein attempting to decode the ECC comprises attempting to decode the ECC responsively to a given set of the output storage values only when a number of the equations satisfied by the output storage values in the given set is less than a predefined value.

14. The method according to claim 1, wherein reading the sets of the output storage values comprises:

reading a first set of the output storage values using a given setting of the read parameters;

adjusting at least one of the read parameters in a given direction;

reading a second set of the output storage values using the adjusted read parameters;

making a comparison between a first number of the equations satisfied by the first set of the output storage values and a second number of the equations satisfied by the second set of the output storage values; and

responsively to the comparison, determining whether to reverse the given direction for reading at least one subsequent set of the output storage values.

15. The method according to claim 1, wherein reading the output storage values comprises determining soft metrics for at least some of the read output storage values, wherein determining the numbers of the satisfied equations comprises computing, based on the soft metrics, respective reliability measures of the equations with respect to each of the sets of the output storage values, and wherein identifying the preferred setting of the read parameters comprises selecting the preferred setting based on the reliability measures of the equations.

16. The method according to claim 1, wherein reading the output storage values comprises determining Log Likelihood Ratios (LLRs) for at least some of the read output storage values, wherein determining the numbers of the satisfied equations comprises substituting respective signs of the LLRs into the equations, and wherein identifying the preferred setting of the read parameters comprises selecting the preferred setting based on the numbers of the equations that are satisfied when the signs of the LLRs are substituted therein.

17. The method according to claim 1, wherein the reading parameters comprise a time that elapsed since the encoded data was stored in the group of the memory cells.

18. The method according to claim 1, wherein the reading parameters comprise a statistical property of a noise that distorts the output storage values.

19. The method according to claim 1, wherein the memory cells are comprised in a memory device, and wherein the preferred setting is identified at a controller that is separate from the memory device.

20. The method according to claim 19, wherein identifying the preferred setting comprises sending from the controller to the memory device a command to apply the preferred setting.

21. The method according to claim 19, wherein identifying the preferred setting comprises sending from the controller to the memory device a notification related to a given set of the output storage values, so as to cause the memory device to read another set of the output storage values.

22. The method according to claim 21, wherein sending the notification comprises indicating to the memory device a failure to decode the ECC based on the given set of the output storage values.

23. Apparatus for operating a memory that includes analog memory cells, the apparatus comprising:

an Error Correction Code (ECC) module, which is operative to encode data with an ECC, which is representable by a plurality of equations; and

circuitry, which is coupled to store the encoded data in a group of the analog memory cells by writing respective input storage values to the memory cells in the group, to read from the memory cells in the group multiple sets of output storage values using one or more different, respective read parameters for each set, to determine respective numbers of the equations that are satisfied by the sets of the output storage values, to identify a preferred setting of the read parameters responsively to the respective numbers of the satisfied equations, and to operate on the memory using the preferred setting of the read parameters.

24. The apparatus according to claim 23, wherein the read parameters comprise read thresholds, and wherein the circuitry is coupled to read the memory cells using the preferred setting of the read thresholds.

25. The apparatus according to claim 23, wherein the read parameters comprise cross-coupling coefficients, and wherein the circuitry is coupled to cancel cross-coupling interference in the output storage values using the preferred setting of the cross-coupling coefficients.

26. The apparatus according to claim 23, wherein the ECC comprises a binary ECC, and wherein the equations comprise Boolean equations.

27. The apparatus according to claim 23, wherein the ECC comprises a linear ECC, and wherein the equations comprise parity check equations.

28. The apparatus according to claim 23, wherein the circuitry is coupled to select the one or more read parameters that correspond to a set of the output storage values that satisfies a maximum number of the equations.

29. The apparatus according to claim 23, wherein the circuitry is coupled to process a set of the output storage values read using the preferred setting of the read parameters so as to decode the ECC.

30. The apparatus according to claim 23, wherein a number of the satisfied equations at the preferred setting of the read parameters is less than a total number of the equations in the plurality.

31. The apparatus according to claim 23, wherein the circuitry is coupled to identify the preferred setting by selecting the setting of the read parameters at which all of the equations in the plurality are satisfied.

32. The apparatus according to claim 23, wherein the circuitry is coupled to cause the ECC module to attempt decoding the ECC responsively to each of the sets of the output storage values.

33. The apparatus according to claim 32, wherein the circuitry is coupled to identify the preferred setting by selecting the setting of the read parameters at which the ECC is decoded successfully.

34. The apparatus according to claim 32, wherein the ECC module is operative to attempt decoding the ECC by modifying the sets of the output storage values to produce respective modified sets of the output storage values, and wherein the circuitry is coupled to select the preferred setting responsively to respective modified numbers of the equations that are satisfied by the modified sets of the output storage values.

35. The apparatus according to claim 32, wherein the circuitry is coupled to cause the ECC module to attempt decoding the ECC responsively to a given set of the output storage values only when a number of the equations satisfied by the output storage values in the given set is less than a predefined value.

36. The apparatus according to claim 23, wherein the circuitry is coupled to read a first set of the output storage values using a given setting of the read parameters, to adjust at least one of the read parameters in a given direction, to read a second set of the output storage values using the adjusted read parameters, to make a comparison between a first number of the equations satisfied by the first set of the output storage values and a second number of the equations satisfied by the second set of the output storage values, and, responsively to the comparison, to determine whether to reverse the given direction for reading at least one subsequent set of the output storage values.

37. The apparatus according to claim 23, wherein the circuitry is coupled to determine soft metrics for at least some of the read output storage values, to compute, based on the soft metrics, respective reliability measures of the equations with respect to each of the sets of the output storage values, and to select the preferred setting based on the reliability measures of the equations.

38. The apparatus according to claim 23, wherein the circuitry is coupled determine Log Likelihood Ratios (LLRs) for at least some of the read output storage values, to substitute respective signs of the LLRs into the equations, and to and to select the preferred setting based on the the numbers of the equations that are satisfied when the signs of the LLRs are substituted therein.

39. The apparatus according to claim 23, wherein the reading parameters comprise a time that elapsed since the encoded data was stored in the group of the memory cells.

40. The apparatus according to claim 23, wherein the reading parameters comprise a statistical property of a noise that distorts the output storage values.

41. The apparatus according to claim 23, wherein the memory cells are comprised in a memory device, and wherein the circuitry comprises:

first circuitry, which is comprised in the memory device and is operative to read the output storage values; and

second circuitry, which is separate from the memory device and is coupled to communicate with the first circuitry over an interface and to identify the preferred setting.

42. The apparatus according to claim 41, wherein the second circuitry is coupled to send over the interface to the first circuitry a command to apply the preferred setting.

43. The apparatus according to claim 41, wherein the second circuitry is coupled to send over the interface to the first circuitry a notification related to a given set of the output storage values, so as to cause the first circuitry to read another set of the output storage values.

44. The apparatus according to claim 43, wherein the second circuitry comprises the ECC module, and wherein the notification comprises an indication of a failure of the ECC module to decode the ECC based on the given set of the output storage values.

45. Apparatus, comprising:

a memory, comprising multiple analog memory cells; and

circuitry, which is operative to encode data with an Error Correction Code (ECC), which is representable by a plurality of equations, to store the encoded data in a group of the analog memory cells by writing respective input storage values to the memory cells in the group, to read from the memory cells in the group multiple sets of output storage values using one or more different, respective read parameters for each set, to determine respective numbers of the equations that are satisfied by the sets of the output storage values, to identify a preferred setting of the read parameters responsively to the respective numbers of the satisfied equations, and to operate on the memory using the preferred setting of the read parameters.