Wake-and-Go Mechanism with Hardware Private Array
First Claim
1. A method, in a data processing system, for performing a wake-and-go operation, the method comprising:
- detecting a thread, executing in a processor, that is waiting for an event that modifies a data value associated with a target address;
populating a wake-and-go storage array with the target address;
storing thread state information in a hardware private array, wherein the hardware private array cannot be addressed by an operating system or work threads running on a processor;
placing the thread in a sleep state; and
responsive to the event that modifies a data value associated with the target address, reloading the thread state information from the hardware private array and placing the thread in a non-sleep state.
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Abstract
A wake-and-go mechanism is provided for a data processing system. When a thread is waiting for an event, rather than performing a series of get-and-compare sequences, the thread updates a wake-and-go array with a target address associated with the event. The wake-and-go mechanism may save the state of the thread in a hardware private array. The hardware private array may comprise a plurality of memory cells embodied within the processor or pervasive logic associated with the bus, for example. Alternatively, the hardware private array may be embodied within logic associated with the wake-and-go storage array.
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Citations
19 Claims
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1. A method, in a data processing system, for performing a wake-and-go operation, the method comprising:
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detecting a thread, executing in a processor, that is waiting for an event that modifies a data value associated with a target address; populating a wake-and-go storage array with the target address; storing thread state information in a hardware private array, wherein the hardware private array cannot be addressed by an operating system or work threads running on a processor; placing the thread in a sleep state; and responsive to the event that modifies a data value associated with the target address, reloading the thread state information from the hardware private array and placing the thread in a non-sleep state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A data processing system, comprising:
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a wake-and-go mechanism; a hardware private array, wherein the hardware private array cannot be addressed by an operating system or work threads running on a processor; and a wake-and-go array, wherein the wake-and-go mechanism is configured to; detect a thread, executing in a processor, that is waiting for an event that modifies a data value associated with a target address; populate the wake-and-go storage array with the target address; store thread state information in the hardware private array, wherein the hardware private array cannot be addressed by an operating system or work threads running on a processor; place the thread in a sleep state; and responsive to the event that modifies a data value associated with the target address, reload the thread state information from the hardware private array and place the thread in a non-sleep state. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A computer program product comprising a computer useable medium having a computer readable program, wherein the computer readable program, when executed on a computing device, causes the computing device to:
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detect a thread, executing in a processor, that is waiting for an event that modifies a data value associated with a target address; populate a wake-and-go storage array with the target address; store thread state information in a hardware private array, wherein the hardware private array cannot be addressed by an operating system or work threads running on a processor; place the thread in a sleep state; and responsive to the event that modifies a data value associated with the target address, reload the thread state information from the hardware private array and place the thread in a non-sleep state. - View Dependent Claims (18, 19)
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Specification