Wake-and-Go Mechanism with Dynamic Allocation in Hardware Private Array

• US 20090199197A1
• Filed: 06/23/2008
• Published: 08/06/2009
• Est. Priority Date: 02/01/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Arimilli, Ravi K., Sharma, Satya P., Swanberg, Randal C.
• Granted Patent: US 8,640,142 B2
• Time in Patent Office: Days
• US Class Current: 718/104
• CPC Class Codes: G06F 2209/521 Atomic
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A wake-and-go mechanism is provided for a data processing system. When a thread is waiting for an event, rather than performing a series of get-and-compare sequences, the thread updates a wake-and-go array with a target address associated with the event. The wake-and-go mechanism may save the state of the thread in a hardware private array. The hardware private array may comprise a plurality of memory cells embodied within the processor or pervasive logic associated with the bus, for example. Alternatively, the hardware private array may be embodied within logic associated with the wake-and-go storage array.

Claims

1. A method, in a data processing system, for performing a wake-and-go operation, the method comprising:

dynamically allocating storage space in a hardware private array for storing thread state information for a thread, wherein the hardware private array cannot be addressed by an operating system or work threads running on a processor;

initiating execution of the thread;

detecting that the thread is waiting for an event that modifies a data value associated with a target address;

populating a wake-and-go storage array with the target address;

storing a state of the thread in the hardware private array;

placing the thread in a sleep state; and

responsive to the event that modifies a data value associated with the target address, reloading the thread state from the hardware private array and placing the thread in a non-sleep state.

2. The method of claim 1, wherein the wake-and-go storage array is a content addressable memory and an address on a bus is used to address the content addressable memory.

3. The method of claim 2, wherein responsive to the event that modifies the data value associated with the target address, the content addressable memory generates an exception.

4. The method of claim 1, wherein the hardware private array comprises a plurality of memory cells embodied within the processor.

5. The method of claim 1, further comprising:

detecting the event that modifies the data value associated with the target address on a bus.

6. The method of claim 5, wherein the hardware private array is embodied within pervasive logic associated with the bus.

7. The method of claim 1, wherein the hardware private array is embodied within logic associated with the wake-and-go storage array.

8. The method of claim 1, wherein the event is an asynchronous event caused by a device outside the processor.

9. (canceled)

10. A data processing system, comprising:

a wake-and-go mechanism;

a hardware private array, wherein the hardware private array cannot be addressed by an operating system or work threads running on a processor; and

a wake-and-go storage array,

wherein an operating system running within the data processing system is configured to;

dynamically allocate space in the hardware private array for thread state information for a thread and initiate execution of the thread; and

wherein the wake-and-go mechanism is configured to;

detect that the thread is waiting for an event that modifies a data value associated with a target address;

populate the wake-and-go storage array with the target address;

store thread state information in the hardware private array;

place the thread in a sleep state; and

responsive to the event that modifies a data value associated with the target address, reload the thread state information from the hardware private array and place the thread in a non-sleep state.

11. The data processing system of claim 10, wherein the wake-and-go storage array is a content addressable memory and an address on a bus is used to address the content addressable memory.

12. The data processing system of claim 11, wherein responsive to the event that modifies the data value associated with the target address, the content addressable memory generates an exception.

13. The data processing system of claim 10, wherein the hardware private array comprises a plurality of memory cells embodied within the processor.

14. The data processing system of claim 10, wherein the wake-and-go mechanism is further configured to detect the event that modifies the data value associated with the target address on a bus.

15. The data processing system of claim 14, wherein the hardware private array is embodied within pervasive logic associated with the bus.

16. The data processing system of claim 10, wherein the hardware private array is embodied within logic associated with the wake-and-go storage array.

17. A computer program product comprising a computer useable medium having a computer readable program, wherein the computer readable program, when executed on a computing device, causes the computing device to:

detect a thread, executing in a processor, that is waiting for an event that modifies a data value associated with a target address;

populate a wake-and-go storage array with the target address;

store thread state information in a hardware private array, wherein the hardware private array cannot be addressed by an operating system or work threads running on a processor and wherein the hardware private array has space dynamically allocated for the thread state information for the thread;

place the thread in a sleep state; and

responsive to the event that modifies a data value associated with the target address, reload the thread state information from the hardware private array and place the thread in a non-sleep state.

18. The computer program product of claim 17, wherein the hardware private array comprises a plurality of memory cells embodied within the processor.

19. The computer program product of claim 17, wherein the hardware private array is embodied within logic associated with the wake-and-go storage array.

20. The computer program product of claim 17, wherein the hardware private array is embodied within pervasive logic associated with a bus.