Silicon carbide semiconductor device including deep layer

• US 20090200559A1
• Filed: 02/12/2009
• Published: 08/13/2009
• Est. Priority Date: 02/13/2008
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Matsuki, Hideo, Okuno, Eiichi, Suzuki, Naohiro
• Granted Patent: US 8,193,564 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A silicon carbide semiconductor device includes a substrate, a drift layer located on a first surface of the substrate, a base region located on the drift layer, a source region located on the base region, a trench penetrating the source region and the base region to the drift layer, a channel layer located in the trench, a gate insulating layer located on the channel layer, a gate electrode located on the gate insulating layer, a source electrode electrically coupled with the source region and the base region, a drain electrode located on a second surface of the substrate, and a deep layer. The deep layer is located under the base region, extends to a depth deeper than the trench and is formed along an approximately normal direction to a sidewall of the trench.

Claims

1. A silicon carbide semiconductor device comprising:

a substrate made of silicon carbide, the substrate having one of a first conductivity type and a second conductivity type, the substrate having first and second opposing surfaces;

a drift layer located on the first surface of the substrate, the drift layer made of silicon carbide, the drift layer having the first conductivity type and having an impurity concentration less than an impurity concentration of the substrate;

a trench provided from a surface of the drift layer;

a gate insulating layer located in the trench;

a base region sandwiching the trench, the base region having a predetermined distance from the gate insulating layer on a sidewall of the trench, the base region made of silicon carbide and having the second conductivity type;

a channel layer located between the base region and the gate insulating layer, the channel layer made of silicon carbide and having the first conductivity type;

a source region located on the base region and sandwiching the trench, the source region being in contact with the channel layer, the source region made of silicon carbide, the source region having the first conductive type and having an impurity concentration greater than the impurity concentration of the drift layer;

a gate electrode located on the gate insulating layer in the trench;

a source electrode electrically coupled with the source region and the base region;

a drain electrode located on the second surface of the substrate; and

a deep layer located under the base region and extending to a depth deeper than the trench, the deep layer formed along an approximately normal direction to the sidewall of the trench, the deep layer having the second conductivity type, wherein

an accumulation channel is provided at the channel layer on the sidewall of the trench and electric current flows between the source electrode and the drain electrode through the source region and the drift layer by controlling a voltage applied to the gate electrode.

2. The silicon carbide semiconductor device according to claim 1, wherein

the deep layer has an impurity concentration greater than or equal to an impurity concentration of the base region.

3. The silicon carbide semiconductor device according to claim 1, further comprising one or more of the deep layers, wherein

the deep layers are located at predetermined intervals.

4. The silicon carbide semiconductor device according to claim 1, further comprising

a current diffusion layer located between the base region and the drift layer, wherein:

the current diffusion layer is made of silicon carbide and has the first conductivity type; and

the current diffusion layer has an impurity concentration greater than or equal to the impurity concentration of the drift layer.

5. The silicon carbide semiconductor device according to claim 4, wherein

the trench penetrating the current diffusion layer to the drift layer.

6. The silicon carbide semiconductor device according to claim 4, wherein

the deep layer penetrating the current diffusion layer and being in contact with the base region.

7. The silicon carbide semiconductor device according to claim 1, wherein

the impurity concentration of the drift layer decreases in a direction from the substrate toward the base region.

8. A silicon carbide semiconductor device comprising:

a substrate made of silicon carbide, the substrate having one of a first conductivity type and a second conductivity type, the substrate having first and second opposing surfaces;

a drift layer located on the first surface of the substrate, the drift layer made of silicon carbide, the drift layer having the first conductivity type and having an impurity concentration less than an impurity concentration of the substrate;

a trench provided from a surface of the drift layer;

a base region sandwiching the trench so as to be in contact with a sidewall of the trench, the base region made of silicon carbide and having the second conductivity type;

a source region located on the base region and sandwiching the trench, the source region being in contact with the sidewall of the trench, the source region made of silicon carbide, the source region having the first conductive type and having an impurity concentration greater than the impurity concentration of the drift layer;

a gate insulating layer located on a surface of the trench;

a gate electrode located on the gate insulating layer in the trench;

a source electrode electrically coupled with the source region and the base region;

a drain electrode located on the second surface of the substrate; and

a deep layer located under the base region and extending to a depth deeper than the trench, the deep layer formed along an approximately normal direction to the sidewall of the trench, the deep layer having the second conductivity type, wherein

an inversion channel is provided at a surface portion of the base region located on the sidewall of the trench and electric current flows between the source electrode and the drain electrode through the source region and the drift layer by controlling a voltage applied to the gate electrode.

9. A silicon carbide semiconductor device comprising:

a substrate made of silicon carbide, the substrate having one of a first conductivity type and a second conductivity type, the substrate having first and second opposing surfaces;

a drift layer located on the first surface of the substrate, the drift layer made of silicon carbide, the drift layer having the first conductivity type and having an impurity concentration less than an impurity concentration of the substrate;

a base region located on the drift layer, the base region made of silicon carbide and having the second conductivity type;

a source region located on the base region, the source region made of silicon carbide, the source region having the first conductive type and having an impurity concentration greater than the impurity concentration of the drift layer;

a trench extending to a depth deeper than the source region and the base region and reaching the drift layer, the trench sandwiched by each of the base region and the source region, the trench provided along a first direction;

a gate insulating layer located on a surface of the trench;

a gate electrode located on the gate insulating layer in the trench;

a source electrode electrically coupled with the source region and the base region;

a drain electrode located on the second surface of the substrate;

a deep layer located under the base region and extending to a depth deeper than the trench, the deep layer formed in parallel with a planer direction of the substrate along a second direction crossing the first direction, the deep layer having the second conductivity type; and

a body layer having a predetermined distance from a sidewall of the trench, the body layer located at a portion deeper than the source region, the body layer having the second conductivity type and having an impurity concentration greater than the impurity concentration of the base region, wherein

an inversion channel is provided at a surface portion of the base region located on the sidewall of the trench and electric current flows between the source electrode and the drain electrode through the source region and the drift layer by controlling a voltage applied to the gate electrode.

10. The silicon carbide semiconductor device according to claim 9, further comprising one or more of the deep layers, wherein:

each of the deep layers has a width of about 1.5 μ

m;

the deep layers are arranged at intervals of about 2.0 μ

m; and

the predetermined distance from the sidewall of the trench and the body layer is between about 0.4 μ

m and about 0.9 μ

m.

11. The silicon carbide semiconductor device according to claim 9, wherein

the impurity concentration of the base region is between about 5.0×

10¹⁵ cm<sup>−

3</sup> and about 5.0×

10¹⁶ cm<sup>−

3</sup>; and

the impurity concentration of the body layer is between about 1.0×

10¹⁸ cm<sup>−

3</sup> and about 1.0×

10²⁰ cm<sup>−

3</sup>.

12. A silicon carbide semiconductor device comprising:

a substrate made of silicon carbide, the substrate having one of a first conductivity type and a second conductivity type, the substrate having first and second opposing surfaces;

a drift layer located on the first surface of the substrate, the drift layer made of silicon carbide, the drift layer having the first conductivity type and having an impurity concentration less than an impurity concentration of the substrate, the drift layer having a cell section and a peripheral section surrounding the cell section;

a base region located on the cell section of the drift layer, the base region made of silicon carbide and having the second conductivity type;

a source region located on the base region, the source region made of silicon carbide, the source region having the first conductive type and having an impurity concentration greater than the impurity concentration of the drift layer;

a plurality of trenches extending to a depth deeper than the source region and the base region and reaching the drift layer, the plurality of trenches arranged in a stripe pattern, each of the plurality of trenches sandwiched by each of the base region and the source region, each of the plurality of trenches provided along a first direction;

a gate insulating layer located on a surface of each of the plurality of trenches;

a gate electrode located on the gate insulating layer in each of the plurality of trenches;

a source electrode electrically coupled with the source region and the base region;

a drain electrode located on the second surface of the substrate;

a deep layer located under the base region and extending to a depth deeper than the plurality of trenches, the deep layer having the second conductivity type, the deep payer having a plurality of stripe portions and an outer edge portion surrounding the plurality of stripe portions, the plurality of stripe portions arranged in a stripe pattern, each of the plurality of stripe portions formed in parallel with a planer direction of the substrate along a second direction crossing the first direction, the outer edge portion of the deep layer located at an outer edge portion of the cell section and formed toward the peripheral section; and

a peripheral high-voltage part located at the peripheral section, wherein

an inversion channel is provided at a surface portion of the base region located on the sidewall of the trench and electric current flows between the source electrode and the drain electrode through the source region and the drift layer by controlling a voltage applied to the gate electrode.

13. The silicon carbide semiconductor device according to claim 12, wherein

the deep layer is formed at a whole area of the outer edge portion of the cell section.

14. The silicon carbide semiconductor device according to claim 12, wherein:

the outer edge portion of the deep layer is at a first distance from the peripheral section;

the plurality of stripe portions of the deep layer is arranged at intervals of a second distance; and

the first distance is less than the second distance.

15. The silicon carbide semiconductor device according to claim 12, wherein:

the outer edge portion of the deep layer has an opening; and

the opening is filled with a depletion layer expanding from the deep layer when the voltage is not applied to the gate electrode.

16. The silicon carbide semiconductor device according to claim 12, wherein:

the peripheral high-voltage part includes a mesa structure portion and a reduced surface field (RESURF) layer;

the mesa structure portion has a recess part deeper than the base region; and

the RESURF layer extends from a bottom surface of the recess part to a predetermined depth and surrounds the cell section.

17. The silicon carbide semiconductor device according to claim 16, wherein:

the deep layer is formed at the whole area of the outer edge portion of the cell section; and

the deep layer is connected with the RESURF layer.

18. The silicon carbide semiconductor device according to claim 16, wherein:

the outer edge portion of the deep layer is at a first distance from the RESURF layer;

the plurality of stripe portions of the deep layer is arranged at intervals of a second distance; and

the first distance is less than the second distance.

19. A silicon carbide semiconductor device comprising:

a substrate made of silicon carbide, the substrate having one of a first conductivity type and a second conductivity type, the substrate having first and second opposing surfaces;

a drift layer located on the first surface of the substrate, the drift layer made of silicon carbide, the drift layer having the first conductivity type and having an impurity concentration less than an impurity concentration of the substrate, the drift layer having a cell section and a peripheral section surrounding the cell section;

a base region located on the cell section of the drift layer, the base region made of silicon carbide and having the second conductivity type;

a source region located on the base region, the source region made of silicon carbide, the source region having the first conductive type and having an impurity concentration greater than the impurity concentration of the drift layer;

a plurality of trenches extending to a depth deeper than the source region and the base region and reaching the drift layer, the plurality of trenches arranged in a stripe pattern, each of the plurality of trenches sandwiched by each of the base region and the source region, each of the plurality of trenches provided along a first direction;

a channel layer located on a surface of each of the plurality of trenches, the channel layer made of silicon carbide, the channel layer having the first conductivity type and having an impurity concentration less than the impurity concentration of the source region;

a gate insulating layer located on a surface of the channel layer in each of the plurality of trenches;

a gate electrode located on the gate insulating layer in each of the plurality of trenches;

a source electrode electrically coupled with the source region and the base region;

a drain electrode located on the second surface of the substrate;

a deep layer located under the base region and extending to a depth deeper than the plurality of trenches, the deep layer having the second conductivity type, the deep payer having a plurality of stripe portions and an outer edge portion surrounding the plurality of stripe portions, the plurality of stripe portions arranged in a stripe pattern, each of the plurality of stripe portions formed in parallel with a planer direction of the substrate along a second direction crossing the first direction, the outer edge portion of the deep layer located at an outer edge portion of the cell section and formed toward the peripheral section; and

a peripheral high-voltage part located at the peripheral section, wherein

an accumulation channel is provided at the channel layer and electric current flows between the source electrode and the drain electrode through the source region and the drift layer by controlling a voltage applied to the gate electrode.