SELF-REPAIRING FIELD EFFECT TRANSISITOR

• US 20090200578A1
• Filed: 02/13/2008
• Published: 08/13/2009
• Est. Priority Date: 02/13/2008
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Xu, Robert
• Granted Patent: US 10,600,902 B2
• Time in Patent Office: Days
• US Class Current: 257/209
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A self repairing field effect transistor (FET) device, in accordance with one embodiment, includes a plurality of FET cells each having a fuse link. The fuse links are adapted to blow during a high current event in a corresponding cell.

Claims

1. A field effect transistor device comprising:

a plurality of field effect transistor cells, wherein each cell includes a corresponding source contact;

a source interconnect; and

a plurality of source fuse links, wherein each given source fuse link couples a given source contact to the source interconnect.

2. The field effect transistor device of claim 1, wherein each source fuse link includes a cavity.

3. The field effect transistor device of claim 1, wherein a corresponding source fuse link blows during a high current event in a defective field effect transistor cell.

4. The field effect transistor device of claim 1, wherein a source fuse link disables a corresponding field effect transistor cell when there is a source-to-drain short in the particular field effect transistor cell.

5. The field effect transistor device of claim 1, wherein a source fuse link disables a corresponding field effect transistor cell when there is a gate-to-source short in the particular field effect transistor cell.

6. The field effect transistor device of claim 1, wherein:

the plurality of source contacts comprise a metal having a relative high melting point; and

the plurality of source fuse links comprise a metal having a relatively low melting point.

7. The field effect transistor device of claim 1, wherein the plurality of field effect transistor cells comprise approximately five hundred to five billion field effect transistor cells.

8. The field effect transistor device of claim 1, wherein the field effect transistor cells comprise planar metal-oxide-semiconductor field effect transistor cells.

9. The field effect transistor device of claim 1, wherein the field effect transistor cells comprise vertical metal-oxide-semiconductor field effect transistor cells.

10. The field effect transistor device of claim 1, wherein the source contacts, source fuse links and source interconnect are aligned in a axis perpendicular to a fabrication surface of the field effect transistor device.

11. An integrated circuit comprising:

a drain region;

a gate region disposed above said drain region, wherein a first portion of the gate region is formed as a first plurality of substantially parallel elongated structures and a second portion of the gate region is formed as a second plurality of substantially parallel elongated structures that are perpendicular to the first plurality of substantially parallel elongated structures;

a plurality of source regions disposed proximate a periphery of the gate region between the first and second plurality of substantially parallel elongated structures;

a plurality of body regions disposed between the drain region and the plurality of source regions and between the first and second plurality of substantially parallel elongated structures;

a gate insulator region disposed between the gate region and the plurality of source regions, between the gate region and the plurality of body regions and between the gate region and the drain region;

a plurality of source contacts, wherein each source contact is coupled to a corresponding source region and body region;

a source interconnect;

a dielectric layer disposed between the plurality of cells and the source interconnect; and

a plurality of source fuse links, wherein each source fuse link couples a given source contact to the source interconnect.

12. The integrated circuit of claim 11, wherein each source fuse link includes a cavity adapted to concentrate heat.

13. The integrated circuit of claim 11, wherein each source fuse link comprises metal having a cavity extending substantially from the corresponding source contact to the source interconnect.

14. The integrated circuit of claim 11, wherein each source fuse link comprises metal having a cavity substantially in a middle of the source fuse link.

15. The integrated circuit of claim 11, wherein each source fuse link comprises metal and is adapted to be blown by a failure mode level of current.

16. A method of fabricating a field effect transistor device comprising:

forming a plurality of field effect transistor cells, wherein each cell includes a source region;

forming a plurality of source contacts, wherein each given source contact is coupled to a corresponding source region;

forming a source interconnect; and

forming a plurality of source fuse links, wherein each source fuse link is coupled between a corresponding source contact and the source interconnect; and

17. The method according to claim 16, wherein the plurality of source fuse links comprise one or more metals selected from the group consisting of copper, aluminum, bismuth, indium and tin.

18. The method according to claim 17, wherein the plurality of source contacts comprise one or more metals selected from the group consisting of tantalum, titanium, tungsten, titanium nitride, tantalum nitride, and titanium silicide.

19. The method according to claim 17, wherein each source fuse link includes a cavity.

20. The method according to claim 16, wherein the plurality of source contacts comprise one or more metals selected from the group consisting of tantalum, titanium, tungsten, titanium nitride, tantalum nitride, and titanium silicide.