SEMICONDUCTOR DEVICE HAVING MOS-TRANSISTOR FORMED ON SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING THEREOF

• US 20090200593A1
• Filed: 01/28/2009
• Published: 08/13/2009
• Est. Priority Date: 01/30/2008
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: UCHIYAMA, Hiroyuki
• Granted Patent: US 8,013,373 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A semiconductor device comprises MOS transistors sequentially arranged in the plane direction of a substrate, wherein a gate electrode and a wiring portion for connecting between the gate electrodes to each other are implanted into a layer that is lower than a surface of the substrate in which a diffusion layer has been formed. A first device isolation area with a STI structure for separating the diffusion layers that function as a source/drain area is formed on the surface of the substrate. A second device isolation area with the STI structure for separating channel areas of the MOS transistors adjacent to each other is formed in a layer that is lower than a layer that has the first device isolation area.

Claims

1. A semiconductor device, comprising MOS transistors sequentially arranged in a plane direction of a substrate,

wherein a gate electrode and a wiring portion for connecting between the gate electrodes to each other are disposed into a layer lower than a surface of the substrate in which a diffusion layer has been formed.

2. The semiconductor device according to claim 1, further comprising:

a first device isolation area for separating the diffusion layers that function as a source/drain area of the MOS transistors adjacent to each other on the surface of the substrate; and

a second device isolation area for separating channel areas of the MOS transistors adjacent to each other in a layer that is lower than a layer that has the first device isolation area.

3. The semiconductor device according to claim 2, further comprising capacitors

wherein each of the capacitors is connected to one of the source/drain areas of associated MOS transistors, the capacitor and the MOS transistor functioning as a memory cell.

4. A semiconductor device, comprising:

a substrate;

a plurality of MOS transistors each having a gate electrode disposed under a top surface of the substrate;

a wiring layer for connecting between the gate electrodes, the wiring layer being disposed under the top surface of the substrate, and the wiring layer extending in a first direction;

a first isolation region formed in the substrate for separating source/drain areas of the MOS transistors adjacent to each other in the first direction; and

a second isolation region formed in the substrate for separating channel areas of the MOS transistors adjacent to each other in the first direction,

wherein the second isolation region is disposed under the wiring layer.

5. The semiconductor device according to claim 4,

wherein two MOS transistors adjacent to each other in a second direction orthogonal to the first direction share a source/drain area disposed between said two MOS transistors.

6. The semiconductor device according to claim 5, further comprising:

a bit line connected to the source/drain area disposed between said two MOS transistors; and

two capacitors connected each to one of the other source/drain areas which are not shared by said two MOS transistors.

7. The semiconductor device according to claim 4, further comprises a third isolation region formed in the substrate for separating source/drain areas of the MOS transistors adjacent to each other in a second direction orthogonal to the first direction.

8. A method for manufacturing a semiconductor device comprising MOS transistors sequentially arranged in a plane direction of a substrate, comprising:

forming a first device isolation area for separating diffusion layers that function as a source/drain area of the MOS transistors adjacent to each other on a surface of the substrate; and

forming a second device isolation area for separating channel areas of the MOS transistors adjacent to each other in a layer that is lower than a layer that has the first device isolation area.

9. The method for manufacturing a semiconductor device according to claim 8, wherein, in order to form the first and second device isolation areas, the method comprising:

forming parallel first trench patterns by etching the surface of the substrate; and

forming parallel second trench patterns perpendicular to the first trench patterns by etching the substrate surface in which the first trench patterns were formed.

10. The method for manufacturing a semiconductor device according to claim 9, further comprising:

forming the first and second trench patterns in a linear shape.

11. The method for manufacturing a semiconductor device according to claim 9, further comprises forming gate electrodes and a wiring layer disposed facing to a surface of the first trench patterns with an intervention of a gate insulating film therebetween,

wherein the wiring layer connects the gate electrodes to each other.

12. The method for manufacturing a semiconductor device according to claim 9,

wherein the second device isolation area is formed by disposing an insulating material at a cross area of the first trench pattern and the second trench pattern.