Split-gate nonvolatile semiconductor memory device

• US 20090200597A1
• Filed: 02/10/2009
• Published: 08/13/2009
• Est. Priority Date: 02/13/2008
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Sakai, Isami
• Granted Patent: US 8,035,155 B2
• Time in Patent Office: Days
• US Class Current: 257/320
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A nonvolatile semiconductor memory device includes a floating gate; an erasing gat; and a control gate. The floating gate is provided on a channel region of a semiconductor substrate through a first insulating layer. The erasing gate is provided on the floating gate through a second insulating layer. The control gate is provided beside the floating gate and the erasing gate through a third insulating layer. The floating gate is U-shaped.

Claims

1. A nonvolatile semiconductor memory device, comprising:

a floating gate configured to be provided on a channel region of a semiconductor substrate through a first insulating layer;

an erasing gate configured to be provided on said floating gate through a second insulating layer; and

a control gate configured to be provided beside said floating gate and said erasing gate through a third insulating layer,

wherein said floating gate is U-shaped.

2. The nonvolatile semiconductor memory device according to claim 1, wherein said floating gate faces said erasing gate at both ends of said U-shaped through said second insulating layer.

3. The nonvolatile semiconductor memory device according to claim 1, wherein in said second insulating layer, a thickness of a portion contacting with each of both ends of said U-shaped is larger than a thickness of other portions.

4. The nonvolatile semiconductor memory device according to claim 1, wherein in said second insulating layer, a thickness of a portion contacting with one of both ends of said U-shaped is larger than a thickness of a portion contacting with the other of said both ends.

12. The nonvolatile semiconductor memory device according to claim 1, wherein said third insulating layer includes:

a lamination layer configured to include a silicon oxide film and a silicon nitride film.

13. The nonvolatile semiconductor memory device according to claim 1, further comprising:

source drain regions configured to be provided on both sides of said channel region;

a first silicide layer configured to be provided on one of said source drain regions;

a second silicide layer configured to be provided on the other of said source drain regions; and

a third silicide layer configured to be provided on said control gate.

5. A nonvolatile semiconductor memory device, comprising:

a floating gate configured to be provided on a channel region of a semiconductor substrate through a first insulating layer;

an erasing gate configured to be provided on said floating gate through a second insulating layer; and

a control gate configured to be provided beside said floating gate and said erasing gate through a third insulating layer,

wherein said floating gate includes;

a bottom surface portion configured to contact with said first insulating layer,

a first side portion configured to be connected to one end of said bottom surface portion at one end, and extend toward a direction away from a surface of said semiconductor substrate, and

a second side portion configured to be connected to the other end of said bottom surface portion at one end, and extend toward said direction away from said surface of said semiconductor substrate.

6. The nonvolatile semiconductor memory device according to claim 5, wherein said floating gate faces said erasing gate at the other end of said first side portion and the other end of said second side portion through said second insulating layer.

7. The nonvolatile semiconductor memory device according to claim 5, wherein in said second insulating layer, a thickness of a portion contacting with said bottom surface portion is larger than a thickness of a portion contacting with each of the other end of said first side portion and the other end of said second side portion.

8. The nonvolatile semiconductor memory device according to claim 5, wherein in said second insulating layer, a thickness of a portion contacting with one of the other end of said first side portion and the other end of said second side portion is larger than a thickness of a portion contacting with the other of said the other end of said first side portion and said the other end of said second side portion.

14. The nonvolatile semiconductor memory device according to claim 5, wherein said third insulating layer includes:

a lamination layer configured to include a silicon oxide film and a silicon nitride film.

15. The nonvolatile semiconductor memory device according to claim 5, further comprising:

source drain regions configured to be provided on both sides of said channel region;

a first silicide layer configured to be provided on one of said source drain regions;

a second silicide layer configured to be provided on the other of said source drain regions; and

a third silicide layer configured to be provided on said control gate.

9. A nonvolatile semiconductor memory device, comprising:

a floating gate configured to be provided on a channel region of a semiconductor substrate through a first insulating layer;

an erasing gate configured to be provided on said floating gate through a second insulating layer; and

a control gate configured to be provided beside said floating gate and said erasing gate through a third insulating layer,

wherein said floating gate is L-shaped.

10. The nonvolatile semiconductor memory device according to claim 9, wherein said floating gate faces said erasing gate at one end of said L-shaped through said second insulating layer.

11. The nonvolatile semiconductor memory device according to claim 10, wherein in said second insulating layer, a thickness of a portion contacting with a portion facing said first insulating layer in said floating gate is larger than a thickness of a portion contacting with a portion facing said erasing gate in said floating gate.

16. The nonvolatile semiconductor memory device according to claim 9, wherein said third insulating layer includes:

a lamination layer configured to include a silicon oxide film and a silicon nitride film.

17. The nonvolatile semiconductor memory device according to claim 9, further comprising:

source drain regions configured to be provided on both sides of said channel region;

a first silicide layer configured to be provided on one of said source drain regions;

a second silicide layer configured to be provided on the other of said source drain regions; and

a third silicide layer configured to be provided on said control gate.