POWER MOSFET

• US 20090200607A1
• Filed: 01/28/2009
• Published: 08/13/2009
• Est. Priority Date: 02/08/2008
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: MATSUURA, Naoki
• Application Number:
  US12/361,067
• Publication Number:
  US 20090200607A1
• Time in Patent Office: Days
• US Class Current: 257/332
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power MOSFET of the invention includes a cell region in which a plurality of cells constituted of a transistor having a gate electrode formed in a trench is aligned, the plurality of cells being arranged to form a square grid and a gate interconnect lead formed so as to extend out of the cell region, with an end portion overlapping an outermost peripheral gate electrode in the cell region for connection.

Claims

1. A power MOSFET comprising:

a cell region in which a plurality of cells constituted of a transistor having a gate electrode formed in a trench is aligned, the plurality of cells being arranged to form a square grid; and

a gate interconnect lead formed so as to extend out of said cell region, with an end portion overlapping an outermost peripheral gate electrode in said cell region for connection.

2. The power MOSFET according to claim 1, wherein said gate interconnect lead is formed so as to surround said cell region.

3. The power MOSFET according to claim 1, wherein said gate interconnect lead overlaps said outermost peripheral gate electrode for connection, by generally a widthwise half portion of said outermost peripheral gate electrode.

4. The power MOSFET according to claim 1, wherein said outermost peripheral gate electrode and said gate interconnect lead are of a same type conductor.

5. The power MOSFET according to claim 1, wherein a width of said outermost peripheral gate electrode is in a range of twice to five times of that of other gate electrodes.

6. The power MOSFET according to claim 5, wherein a width of said outermost peripheral gate electrode is in a range of 2 to 5 μ

m.