Phase Interpolator System and Associated Methods

• US 20090201064A1
• Filed: 02/11/2008
• Published: 08/13/2009
• Est. Priority Date: 02/11/2008
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Ferrsiolo, Frank D., Coteus, Paul W., Dreps, Daniel M., Kim, Kyu-hyoun
• Granted Patent: US 8,004,335 B2
• Time in Patent Office: Days
• US Class Current: 327/299
• CPC Class Codes: H03B 27/00 Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs
• CPC Class Codes: H03H 11/22 providing two or more phase shifted output signals, e.g. n-phase output
• CPC Class Codes: H03H 7/21 providing two or more phase shifted output signals, e.g. n-phase output
• CPC Class Codes: H03K 2005/00052 by mixing the outputs of fixed delayed signals with each other or with the input signal
• CPC Class Codes: H03K 2005/00065 by current control, e.g. by parallel current control transistors
• CPC Class Codes: H03K 2005/00293 Output pulse is a delayed pulse issued after a rising or a falling edge, the length of the output pulse not being in relation with the length of the input triggering pulse
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H03K 5/15026 with asynchronously driven series connected output stages

Abstract

A phase interpolator system is disclosed that may include a clock to provide a clock signal, and a control section in communication with the clock to regulate the strength of the clock signal. The system may also include a generator circuit to produce an alternate clock signal based upon the strength of the clock signal received from the control section.

Claims

1. A phase interpolator system comprising:

a clock to provide a clock signal;

a control section in communication with said clock to regulate the strength of the clock signal; and

a generator circuit to produce an alternate clock signal based upon the strength of the clock signal received from said control section.

2. The phase interpolator system of claim 1 wherein said control section includes at least one of a passive circuit element and an active circuit element.

3. The phase interpolator system of claim 2 wherein said passive circuit element includes at least one of a variable resistor, a variable capacitor, and a variable inductor.

4. The phase interpolator system of claim 2 wherein said active circuit element includes at least one of a variable buffer, a variable inverter, and a multiplexer.

5. The phase interpolator system of claim 1 wherein said generator circuit includes at least one of a poly-phase filter, a resistor-capacitor multi-pole poly-phase filter, a quadrature oscillator, an open loop quadrature oscillator, and a complementary metal-oxide-semiconductor open loop quadrature oscillator.

6. The phase interpolator system of claim 1 wherein said control section includes a weighting circuit.

7. The phase interpolator system of claim 6 wherein said weighting circuit includes at least one of a weighted inverter stage and a variable buffer.

8. The phase interpolator system of claim 1 said control section includes a phase rotation controller.

9. The phase interpolator system of claim 1 wherein said clock provides digital clock signals.

10. The phase interpolator system of claim 1 wherein said clock provides a clock signal having one phase.

11. A method to improve a phase interpolator system comprising:

providing a clock signal;

regulating the strength of the clock signal; and

producing an alternate clock signal based upon the strength of the clock signal.

12. The method of claim 11 wherein regulating the strength of the clock signal uses at least one of a passive circuit element and an active circuit element.

13. The method of claim 12 wherein the passive circuit element includes at least one of a variable resistor, a variable capacitor, and a variable inductor.

14. The method of claim 12 wherein the active circuit element includes at least one of a variable buffer, a variable inverter, and a multiplexer.

15. The method of claim 11 wherein producing the alternate clock signal uses at least one of a poly-phase filter, a resistor-capacitor multi-pole poly-phase filter, a quadrature oscillator, an open loop quadrature oscillator, and a complementary metal-oxide-semiconductor open loop quadrature oscillator.

16. The method of claim 11 wherein regulating the strength of the clock signal is performed by a weighting circuit.

17. The method of claim 11 wherein the weighting circuit includes at least one of a weighted inverter stage and a variable buffer.

18. The method of claim 11 wherein the clock provides at least one of digital clock signals and a single phase clock signal.

20. The computer program product of claim 18 further comprising program code configured to:

use a weighting circuit to regulate the strength of the clock signal.

19. A computer program product embodied in a tangible media comprising:

computer readable program codes coupled to the tangible media to improve a phase interpolator system, the computer readable program codes configured to cause the program to;

provide a clock signal;

regulate the strength of the clock signal; and

produce an alternate clock signal based upon the strength of the clock signal.